SN54LVTH652, SN74LVTH652

3.3V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3STATE OUTPUTS

SCBS706F − AUGUST 1997 − REVISED OCTOBER 2003

2

POST OFFICE BOX 655303

description/ordering information (continued)

The ’LVTH652 devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for

multiplexed transmission of data directly from the data bus or from the internal storage registers.

Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB

and SBA) inputs are provided to select whether real-time or stored data is transferred. The circuitry used for

select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between

real-time and stored data. A low input selects real-time data and a high input selects stored data. Figure 1

illustrates the four fundamental bus-management functions that can be performed with the ’LVTH652 devices.

Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at

the appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB

and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops

by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input; therefore,

when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains

at its last state.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup

or pulldown resistors with the bus-hold circuitry is not recommended.

and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by

the current-sinking/current-sourcing capability of the driver.

disables the outputs, preventing damaging current backflow through the device when it is powered down. The

power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,

which prevents driver conflict.

FUNCTION TABLE

INPUTS

DATA I/O†

OPERATION OR FUNCTION

OEAB

OEBA

CLKAB

CLKBA

SAB

SBA

A1−A8

B1−B8

OPERATION OR FUNCTION

L

H

H or L

H or L

X

X

Input

Input

Isolation

L

H

↑↑

X

X

Input

Input

Store A and B data

X

H

↑

H or L

X

X

Input

Unspecified‡

Store A, hold B

H

H

↑↑

X‡

X

Input

Output

Store A in both registers

L

X

H or L

↑

X

X

Unspecified‡

Input

Hold A, store B

L

L

↑↑

XX‡

Output

Input

Store B in both registers

L

L

X

X

X

L

Output

Input

Real-time B data to A bus

L

L

X

H or L

X

H

Output

Input

Stored B data to A bus

H

H

X

X

L

X

Input

Output

Real-time A data to B bus

H

H

H or L

X

H

X

Input

Output

Stored A data to B bus

H

L

H or L

H or L

H

H

Output

Output

Stored A data to B bus and

stored B data to A bus

† The data-output functions can be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions always are

enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.

‡ Select control = L; clocks can occur simultaneously.

Select control = H; clocks must be staggered to load both registers.