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TPS40180 Datasheet(PDF) 32 Page - Texas Instruments |
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TPS40180 Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 52 page  www.ti.com LAYOUT CONSIDERATIONS Power Stage Device Peripheral TPS40180 SLVS753B – FEBRUARY 2007 – REVISED NOVEMBER 2007 A synchronous BUCK power stage has two primary current loops. One is the input current loop which carries high AC discontinuous current adn the other is the output current loop carrying a high DC continuous current. The input current loop includes the input capacitors, the main switching MOSFET, the inductor, the output capacitors and the ground path back to the input capacitors. To keep this loop as small as possible, it is generally good practice to place some ceramic capacitance directly between the drain of the main switching MOSFET and the source of the synchronous rectifier (SR) through a power ground plane directly under the MOSFETs. The output current loop includes the SR MOSFET, the inductor, the output capacitors, and the ground return between the output capacitors and the source of the SR MOSFET. As with the input current loop, the ground return between the output capacitor ground and the source of the SR MOSFET should be routed under the inductor and SR MOSFET to minimize the power loop area. The SW node area should be as small as possible to reduce the parasitic capacitance and minimize the radiated emissions. The gate drive loop impedance (HDRV-gate-source-SW and LDRV-gate-source- GND) should be kept to as low as possible. The HDRV and LDRV connections should widen to 20mils as soon as possible out from the IC pin. The TPS40180 provides separate signal ground (GND) and power ground (PGND) pins. It is required to separate properly the circuit grounds. The return path for the pins associated with the power stage should be through PGND. The other pins especially for those sensitive pins such as FB, RT and ILIM should be through the low noise GND. The GND and PGND plane are suggested to be connected at the output capacitor with single 20 mil trace. A minimum 0.1- µF ceramic capacitor must be placed as close to the VDD pin and AGND as possible with at least 15 mil wide trace from the bypass capacitor to the GND. A 4.7- µF ceramic capacitor should be placed as close to the PVCC pin and PGND as possible. BP5 is the filtered input from the PVCC pin. A 4.7- Ω resistor should be connected between PVCC and BP5 and a 1- µF ceramic capacitor should be connected from BP5 to GND. Both components should be as close to BP5 pin as possible. When a DCR sensing method is applied, the sensing resistor is placed close to the SW node. It is connected to the inductor with Kelvin connection. The sensing traces from the power stage to the chip should be away from the switching components. The sensing capacitor should be placed very close to the CS+ and CS- pins. The frequency setting resistor should be placed as close to RT pin and GND as possible. The VOUT and GSNS pins should be directly connected to the point of load where the voltage regulation is required. A parallel pair of 10-mil traces connects the regulated voltage back to the chip. They should be away from the switching components. The PowerPAD should be electrically connected to GND. 32 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40180 |
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