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TPS40180 Datasheet(PDF) 30 Page - Texas Instruments |
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TPS40180 Datasheet(HTML) 30 Page - Texas Instruments |
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30 / 52 page  www.ti.com 2 DIFFO FB 1 5 VSH 7 8 RT VDD 24 SS 19 CLKIO 21 15 TPS40180 CLK Master PSEL 2 DIFFO FB 1 5 VSH 24 19 CLKIO TPS40180 CLK Slave COMP COMP 10 kW 2 DIFFO FB 1 5 VSH 7 8 RT VDD 24 SS 19 CLKIO 21 15 TPS40180 CLK Slave PSEL COMP 7 8 RT VDD SS 21 15 PSEL UDG-07034 TPS40180 SLVS753B – FEBRUARY 2007 – REVISED NOVEMBER 2007 A connection diagram for several controllers sharing phase information and synchronized to each other but having different output voltages is shown in Figure 32. This is similar to the previous example but here the controllers are all control loop masters (SS not pulled to VDD) and control their own output voltages independently. One device is configured as a CLK master (RT not tied to VDD) and is the clock generator for the CLK slaves. Picking the PSEL resistors is the same as before. overcurrent in this configuration depends on which controller senses the overcurrent event. If one of the CLK slaves experiences a fault, that converter only shuts down, and enter the hiccup restart mode. If the CLK master controller senses an overcurrent, it stops sending CLKIO pulses to the slaves, causing them to stop. The master then enters a hiccup recovery mode. Figure 32. Phase Share Multiple Output Configuration 30 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40180 |
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