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TPS40180 Datasheet(PDF) 25 Page - Texas Instruments |
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TPS40180 Datasheet(HTML) 25 Page - Texas Instruments |
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25 / 52 page  www.ti.com VDD UVLO > 2.5 V PGOOD 20 V Settle Time V VDD+2 V V VDD+4 V V VDD ‘0’ programmed to bit 0 ‘1’ programmed to bit 1 >=15 ms 15 ms write EEPROM 1ms >8ms A5 A4 A3 A2 A1 A0 D A5 A4 A3 A2 A1 A0 D 1ms >10ms UDG-07032 0 0 0 0 1 1 1 A5 A4 A3 A2 A1 A0 D UDG-07038 100 ns ‘0’ 900 ns 1 ms ‘1’ UDG-07037 Using the Device for Clock Master/Slave Operation TPS40180 SLVS753B – FEBRUARY 2007 – REVISED NOVEMBER 2007 Figure 28. eTrim™ EEPROM Programming Sequence The pulses from VVDD + 2 V to VVDD + 4 V on UVLO are governed by the timing shown in Figure 29. Note that there are six address bits in the sequence to write to a single EEPROM bit. To write to the eTrim™ accessible bits, the address sequence must be correct for all six bits or else the write attempt has no effect. To write to eTrim™ accessible bits the first four address bits must be zero. Anything else is not accepted. Address bits A1 and A0 select which eTrim™ accessible EEPROM bit is written. For example, to write a 1 to bit 3 of the eTrim™ accessible bits, the data pulse sequence would look like Figure 30. Figure 29. eTrim™ Bit Pulse Timing Figure 30. Write 1 to Bit 3 As data is clocked into the device, the reference voltage reflects the updates without writing the data buffer to the actual EEPROM. System measurements can be made after a suitable system dependent settling time has elapsed after changing the bits in the buffer. When satisfied with the results, the EEPROM may be written by pulling PGOOD to 20 V and UVLO to V(VDD) + 4 V for at least 15 ms. For best reliability, the EEPROM should only be written to by pulling PGOOD to 20V and UVLO to V(VDD) + 4V a maximum of three times during the product lifetime. This writing only needs to be done once during the entire trimming cycle, after the optimal trim values are found since data clocked in will affect the output without perfoming the actual write. Until written, changes are not permanent and will be lost after power cycling the device. The TPS40180 can be operated as either a master clock source or a slave to a master clock. Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Link(s): TPS40180 |
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