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TPS40180 Datasheet(PDF) 24 Page - Texas Instruments |
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TPS40180 Datasheet(HTML) 24 Page - Texas Instruments |
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24 / 52 page  www.ti.com TPS40180 SLVS753B – FEBRUARY 2007 – REVISED NOVEMBER 2007 of nominal so further trim is not necessary unless it is desired to further reduce total system errors. This factory trim uses the same eTrim™ mechanism that can be used at the system or converter level and changes the same bits that the user changes if using eTrim™. Consequently, not all of the trim range may be available to make adjustments in system as the factory trim sets the bits to the value that provides the correct nominal reference voltage. Typically, the trim has at least 3 steps remaining in any direction to allow for user system level trim. There are several steps required to use the eTrim™ feature. A typical trim sequence would flow as follows: 1. Power up the system and wait for the system to stabilize in steady state 2. Program the TPS40180 reference trim to a default setting (overwriting factory trim) 3. Measure the system output voltage 4. Calculate a correction factor to be applied to the output voltage 5. Program the EEPROM inside the TPS40180 with the new trim code 6. Measure the new system output voltage 7. Repeat from step 4 if required The TPS40180 provides 4 trim bits available for user programming. The bits and their effect on the untrimmed reference value are given in Table 1. Table 1. eTrim Bit Codes and Effect eTrim™ REFERENCE BIT CODE REFERENCE CHANGE (mV) b3 b2 b1 b0 1 0 0 0 +14 1 0 0 1 +12 1 0 1 0 +10 1 0 1 1 +8 1 1 0 0 +6 1 1 0 1 +4 1 1 1 0 +2 1 1 1 1 0(1) 0 0 0 0 0 0 0 0 1 –2 0 0 1 0 –4 0 0 1 1 –6 0 1 0 0 –8 0 1 0 1 –10 0 1 1 0 –12 0 1 1 1 –14 (1) Default setting The process of writing to the on chip trim EEPROM is as follows. With power applied to the system and the system in steady state: 1. Force the input voltage to the device, VVDD, to a level of 7 V (this eases stresses on the UVLO pin). 2. Raise the UVLO pin to a level 2 V above VVDD and PGOOD to 20 V 3. Apply a pulse of VVDD + 4V for a minimum of 10 µs to UVLO 4. Bring UVLO to VVDD + 2 V for at least 8 µs 5. The UVLO pin is then pulsed to VVDD + 4 V seven times (six address bits and one data bit) for each bit that is to be written. The pulse period is typically 1 µs and the width of the pulse determines whether the pulse is interpreted as a 1 or as a 0 by the EEPROM circuitry. 6. Data has been placed in a buffer. To finalize the writing, pull PGOOD to 20 V and the UVLO pin to VVDD + 4 V for at least 15 ms. Figure 28 shows a typical sequence. 24 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40180 |
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