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TPS40180 Datasheet(PDF) 23 Page - Texas Instruments

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Part No. TPS40180
Description  SINGLE PHASE STACKABLE CONTROLLER
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TPS40180 Datasheet(HTML) 23 Page - Texas Instruments

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PGOOD Functionality
Output Overvoltage and Undervoltage Protection
Overtemperature Protection
eTRIM™
TPS40180
SLVS753B – FEBRUARY 2007 – REVISED NOVEMBER 2007
PGOOD functions as a normal open drain power good output on an device configured as a master. This is an
open drain signal and pulls low when any condition exists that would indicate that the output of the supply might
be out of regulation. These conditions include:
• FB pin more that ±15% from nominal
• soft-start is active
• A UVLO condition exists for the TPS40180
• The TPS40180 has detected a short circuit condition
• The TPS40180 die is over warning temperature threshold (115°C)
If the device is configured as a voltage loop slave, PGOOD pulls low the following conditions only:
• A UVLO condition exists for the TPS40180
• The TPS40180 die is over warning temperature threshold (115°C)
Note that when there is no power to the device, PGOOD is not able to pull close to GND if an auxiliary supply is
used for the power good indication.
If the output voltage is sensed to be too low, the TPS40180 turns off the power FETs, and initiate a hiccup restart
sequence just as if a fault condition had occurred. The sensing of the output voltage is done using the FB pin
and the undervoltage threshold voltage for the FB pin is 580-mV typical. The pre-bias circuitry is reset at this time
and the restart does not discharge an output pre-bias condition if it exists.
The TPS40180 also includes an output overvoltage protection mechanism. This mechanism is designed to turn
on the low-side FET when the FB pin voltages exceeds the overvoltage protection threshold of 810-mV (typical).
The high side FET turns off and the low-side FET turns on and stays on until the voltage on the FB drops below
the undervoltage threshold. At this point, the controller enters a hiccup recovery cycle as in the undervoltage
case. The output overvoltage protection scheme is active at all times. If at any time when the controller is
enabled, the FB pin voltage exceeds the overvoltage threshold, the low-side FET turns on until the FB pin
voltage falls below the undervoltage threshold.
When the TPS40180 die temperature exceeds 115
°C, the PG pin is pulled low as a warning that temperatures
are becoming excessive. Systems can act on this indication as appropriate.
The TPS40180 shuts down if the die temperature is sensed to be more than 135
°C. The die must cool to less
than the warning level reset of 105
°C before the device restarts. The device restarts automatically after the die
cools to this level.
The TPS40180 incorporates an innovative new feature that allows the user to trim the reference voltage in
system. This allows the user to tighten overall output tolerances by trimming out errors caused by resistor divider
and other system tolerances. The reference has been designed so that it may be trimmed without affecting
temperature drift so that the user can perform system level trims without worrying about creating a situation
where the reference temperature drift becomes a problem. Trimming in the TPS40180 is done with a small bank
of EEPROM. Changing bit values in this EEPROM causes parameters, like reference voltage, inside the device
to change. Once trim is accomplished, there is no need to trim again, the change is permanent (but can be
overwritten by subsequent trimming operations). The eTrim™ trimming mechanism has been designed so that
the user can only program the reference voltage so that any errors in the programming sequence does not affect
other factory set trims such as current feedback gain for example. This provides a secure environment for the
user to use and eliminates the possibility that other parameters could inadvertently changed.
The adjustment range is ±14 mV from the untrimmed level. The reference is pre-trimmed at the factory to ±0.5%
Copyright © 2007, Texas Instruments Incorporated
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