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W83781D Datasheet(PDF) 26 Page - Winbond |
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W83781D Datasheet(HTML) 26 Page - Winbond |
26 / 54 page ![]() W83781D/W83781G Publication Release Date: April 14, 2005 - 22 - Revision 2.0 7 6 5 4 3 2 1 0 IN4 -IN5 -IN6 FAN3 Case Open Reserved Reserved Chassis Clear Bit 7: The logical 1 outputs a minimum 20 ms active low pulse on the Case Open pin. The register bit self clears after the pulse has been output. Bit 6-5: Reserved. This bit should be set to 0. Bit 4-0: The logical 1 disables the corresponding interrupt status bit for IRQ interrupt. 8.10 VID/Fan Divisor Register – Index 47h (Bank 0) Register Location: 47h Power on Default Value <7:4> is 0101, <3:0> is 0000 Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 VID0 VID1 VID2 VID3 FAN1 RPM Control FAN1 RPM Control FAN2 RPM Control FAN2 RPM Control Bit 7-6: FAN2 Speed Control. <7:6> = 00 - divide by 1; <7:6> = 01 - divide by 2; <7:6> = 10 - divide by 4; <7:6> = 11 - divide by 8. Bit 5-4: FAN1 Speed Control. <5:4> = 00 - divide by 1; <5:4> = 01 - divide by 2; <5:4> = 10 - divide by 4; <5:4> = 11 - divide by 8. Bit 3-0: The VID <3:0> inputs |
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