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EMC2103-2-AP Datasheet(PDF) 54 Page - SMSC Corporation |
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EMC2103-2-AP Datasheet(HTML) 54 Page - SMSC Corporation |
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54 / 84 page  RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Revision 0.85 (01-29-08) 54 SMSC EMC2103 DATASHEET The EMC2103 contains high limits for all temperature channels. If any measurement meets or exceeds the high limit then the appropriate status bit is set and the ALERT pin is asserted (if enabled). Additionally, the EMC2103 contains low limits for all temperature channels. If the temperature channel drops below the low limit, then the appropriate status bit is set and the ALERT pin is asserted (if enabled). All Limit Registers are Software Locked. 6.20 Fan Setting Registers The Fan Setting Register always displays the current setting of the Fan Driver. Reading from the register will report the current fan speed setting of the fan driver regardless of the operating mode. Therefore it is possible that reading from this register will not report data that was previously written into this register. While the RPM based Fan Speed Control Algorithm or the Look Up Table are active (or both), then the register is read only. Writing to the register will have no affect and the data will not be stored. If both the RPM based Fan Control Algorithm and the Look Up Table are disabled, then the register will be set with the previous value that was used. The register is read / write and writing to this register will affect the fan speed. The contents of the register represent the weighting of each bit in determining the final duty cycle. The output drive for a PWM output is given by Equation [1]. 6.21 PWM Divide Register 39h ** R/W External Diode 2 Low Limit ** Sign 64 32 16 8 4 2 1 00h (0°C) 3Ah ** R/W External Diode 3 Low Limit ** Sign 64 32 16 8 4 2 1 00h (0°C) 3Ch R/W Internal Diode Low Limit Sign 64 32 16 8 4 2 1 00h (0°C) Table 6.27 Fan Driver Setting Register ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 40h R/W Fan Setting 128 64 32 16 8 4 2 1 00h [1] Table 6.28 PWM Divide Register ADDR R/W REGISTER B7B6B5B4 B3B2 B1 B0 DEFAULT 41h R/W PWM Divide 128 64 32 16 8 4 2 1 01h Table 6.26 Limit Registers (continued) ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT Drive VALUE 255 --------------------- ⎝⎠ ⎛⎞ 100% × = |
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