Low-Cost CCFL Controller

8

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CCFL Channel Block Diagram

GATE

DRIVERS

GA

GB

DIGITAL

CCFL

CONTROLLER

CHANNEL FAULT

LAMP FREQUENCY

(40kHz TO 80kHz)

BURST-DIMMING

PWM SIGNAL

CHANNEL ENABLE

MOSFET

GATE DRIVERS

LCM

LAMP CURRENT MONITOR

400mV

2.0V

LAMP OVERCURRENT

LAMP STRIKE AND REGULATION

LAMP OUT

1.0V

1.0V

OVD

OVERVOLTAGE DETECTOR

LAMP MAXIMUM VOLTAGE REGULATION

64 LAMP CYCLE

INTEGRATOR

OVERVOLTAGE

DS3991

Detailed Description

The DS3991 is available for both push-pull and half-

bridge drive topologies. In both drive topologies, the

DS3991 drives two logic-level MOSFETs. The DS3991

alternately turns on the two MOSFETs to create the high-

voltage AC waveform on the secondary. By varying the

duration of the MOSFET turn-on times, the controller is

able to accurately control the amount of current flowing

through the CCFL lamp. See the

Typical Push-Pull

Application and Typical Half-Bridge Application figures.

The DS3991 can also drive more than one CCFL lamp

per channel. The

Typical Push-Pull Application, Multiple

Lamp Per Channel and Typical Half-Bridge Application,

Multiple Lamp Per Channel figures show an application

driving three lamps.

A series resistor on the low-voltage side of the CCFL

lamp enables current monitoring. The voltage developed

across this resistor is fed to the lamp current monitor

(LCM) input on the DS3991. The DS3991 compares the

resistor voltage against an internal reference voltage to

determine the duty cycle for the MOSFET gates. See the

Main System Block Diagram and the CCFL Channel

Block Diagram for more information.

Dimming Control

The DS3991 uses burst dimming to control the lamp

brightness. During the high period of the DPWM cycle,

the lamp is driven at the selected lamp frequency

(40kHz to 80kHz) as shown in Figure 1. This part of the

cycle is also called the burst period because of the

lamp-frequency burst that occurs during this time.

During the low period of the DPWM cycle, the controller

disables the MOSFET gate drivers so the lamp is not

driven. This causes the current to stop flowing in the

lamp, but the time is short enough to keep the lamp

from de-ionizing. Dimming is increased/decreased by

adjusting (i.e., modulating) the burst-period duty cycle.

At the beginning of each burst-dimming cycle, soft-start

slowly ramps the lamp current to reduce the potential to

create audible transformer noise.

There are two methods to control the duty cycle and

frequency of the burst-dimming DPWM. If the PWM_EN

pin is tied low, then the analog-control method is

enabled; a 0V to 3.3V analog voltage at the BRIGHT

input pin determines the duty cycle of a digital pulse-

width modulated (DPWM) signal. The frequency of the

DPWM signal is determined by the value of the resistor

tied from the POSC pin to ground. The slope of the

BRIGHT dimming input is either positive or negative

based on whether the SLOPE pin is tied low or high,

respectively.