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CD54HCT161 Datasheet(PDF) 1 Page - Texas Instruments

Part No. CD54HCT161
Description  High-Speed CMOS Logic Presettable Counters
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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CD54HCT161 Datasheet(HTML) 1 Page - Texas Instruments

 
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Data sheet acquired from Harris Semiconductor
SCHS154D
The CD54HCT161 is obsolete
and no longer is supplied.
Features
• ’HC161, ’HCT161 4-Bit Binary Counter,
Asynchronous Reset
• ’HC163, ’HCT163 4-Bit Binary Counter,
Synchronous Reset
• Synchronous Counting and Loading
• Two Count Enable Inputs for n-Bit Cascading
• Look-Ahead Carry for High-Speed Counting
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
Description
The
’HC161,
’HCT161,
’HC163,
and
’HCT163
are
presettable synchronous counters that feature look-ahead
carry logic for use in high-speed counting applications. The
’HC161 and ’HCT161 are asynchronous reset decade and
binary counters, respectively; the ’HC163 and ’HCT163
devices are decade and binary counters, respectively, that
are reset synchronously with the clock. Counting and
parallel presetting are both accomplished synchronously
with the negative-to-positive transition of the clock.
A low level on the synchronous parallel enable input, SPE,
disables counting operation and allows data at the P0 to P3
inputs to be loaded into the counter (provided that the
setup and hold requirements for SPE are met).
All counters are reset with a low level on the Master Reset
input,
MR.
In
the
’HC163
and
’HCT163
counters
(synchronous reset types), the requirements for setup and
hold time with respect to the clock must be met.
Two count enables, PE and TE, in each counter are
provided for n-bit cascading. In all counters reset action
occurs regardless of the level of the SPE, PE and TE inputs
(and the clock input, CP, in the ’HC161 and ’HCT161
types).
If a decade counter is preset to an illegal state or assumes
an illegal state when power is applied, it will return to the
normal sequence in one count as shown in state diagram.
The look-ahead carry feature simplifies serial cascading of
the counters. Both count enable inputs (PE and TE) must
be high to count. The TE input is gated with the Q outputs
of all four stages so that at the maximum count the terminal
count (TC) output goes high for one clock period. This TC
pulse is used to enable the next cascaded stage.
Ordering Information
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
CD54HC161F3A
-55 to 125
16 Ld CERDIP
CD54HC163F3A
-55 to 125
16 Ld CERDIP
CD54HCT163F3A
-55 to 125
16 Ld CERDIP
CD74HC161E
-55 to 125
16 Ld PDIP
CD74HC161M
-55 to 125
16 Ld SOIC
CD74HC161MT
-55 to 125
16 Ld SOIC
CD74HC161M96
-55 to 125
16 Ld SOIC
CD74HC163E
-55 to 125
16 Ld PDIP
CD74HC163M
-55 to 125
16 Ld SOIC
CD74HC163MT
-55 to 125
16 Ld SOIC
CD74HC163M96
-55 to 125
16 Ld SOIC
CD74HCT161E
-55 to 125
16 Ld PDIP
CD74HCT161M
-55 to 125
16 Ld SOIC
CD74HCT161MT
-55 to 125
16 Ld SOIC
CD74HCT161M96
-55 to 125
16 Ld SOIC
CD74HCT163E
-55 to 125
16 Ld PDIP
CD74HCT163M
-55 to 125
16 Ld SOIC
CD74HCT163MT
-55 to 125
16 Ld SOIC
CD74HCT163M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
February 1998 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
CD54/74HC161, CD54/74HCT161,
CD54/74HC163, CD54/74HCT163
High-Speed CMOS Logic
Presettable Counters
[ /Title
(CD74
HC161
,
CD74
HCT16
1,
CD74
HC163
,
CD74
HCT16
3)
/Sub-
ject
(High
Speed
CMOS
Logic
Preset-
table
Counte
rs)
/Autho
r ()
/Key-
words
(High
Speed
CMOS
Logic
Preset-
table
Counte
rs,
High
Speed


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