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TPS71728DSETG4 Datasheet(PDF) 2 Page - Texas Instruments |
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TPS71728DSETG4 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 27 page www.ti.com ABSOLUTE MAXIMUM RATINGS (1) DISSIPATION RATINGS TPS717xx SBVS068D – FEBRUARY 2006 – REVISED OCTOBER 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION(1) PRODUCT VOUT (2) TPS717xxyyyz XX is nominal output voltage (for example, 28 = 2.8V, 285 = 2.85V, 01 = Adjustable). YYY is package designator. Z is package quantity. (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. (2) Output voltages from 0.9V to 3.3V in 50mV increments are available through the use of innovative factory EEPROM programming; minimum order quantities may apply. Contact factory for details and availability. Over operating temperature range (unless otherwise noted). All voltages are with respect to GND. PARAMETER TPS717xx UNIT Input voltage range, VIN –0.3 to +7.0 V Feedback input voltage range, VFB, VNR –0.3 to +3.6 V Enable voltage range, VEN –0.3 to VIN + 0.3V (2) V Output voltage range, VOUT –0.3 to +7.0 V Maximum output current, IOUT Internally limited Continuous total power dissipation, PDISS See Dissipation Ratings Table Junction temperature range, TJ –55 to +150 °C Storage junction temperature range, TSTG –55 to +150 °C ESD rating, HBM 2 kV ESD rating, CDM 500 V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) VEN absolute maximum rating is VIN + 0.3V or +7.0V, whichever is greater. DERATING FACTOR BOARD PACKAGE RθJC RθJA ABOVE TA = +25°C TA < +25°C TA = +70°C TA = +85°C Low-K(1) DCK 165 °C/W 395 °C/W 2.5mW/ °C 250mW 140mW 100mW High-K(2) DCK 165 °C/W 315 °C/W 3.2mW/ °C 320mW 175mW 130mW Low-K(1) DRV 20 °C/W 140 °C/W 7.1mW/ °C 715mW 395mW 285mW High-K(2) DRV 20 °C/W 65 °C/W 15.4mW/ °C 1540mW 845mW 615mW High-K(2) DSE — 206 °C/W 4.85mW/ °C 485mW 269mW 194mW (1) The JEDEC low-K (1s) board used to derive this data was a 3in × 3in, two-layer board with 2-ounce copper traces on top of the board. (2) The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom of the board. 2 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated |
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