CD54ACT109, CD74ACT109

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SCHS327 – JANUARY 2003

2

POST OFFICE BOX 655303

logic diagram, each flip-flop (positive logic)

PRE

CLK

J

CLR

Q

Q

C

C

C

C

K

TG

TG

TG

TG

C

C

C

C

C

C

–0.5 V to 6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±100 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance,

67

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

M package

73

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

TA = 25°C

–55

°C to

125

°C

–40

°C to

85

°C

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

VCC

Supply voltage

4.5

5.5

4.5

5.5

4.5

5.5

V

VIH

High-level input voltage

2

2

2

V

VIL

Low-level input voltage

0.8

0.8

0.8

V

VI

Input voltage

0

VCC

0

VCC

0

VCC

V

VO

Output voltage

0

VCC

0

VCC

0

VCC

V

IOH

High-level output current

–24

–24

–24

mA

IOL

Low-level output current

24

24

24

mA

∆t/∆v

Input transition rise or fall rate

10

10

10

ns/V

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.