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DS80C310-MCL Datasheet(PDF) 7 Page - Dallas Semiconductor |
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DS80C310-MCL Datasheet(HTML) 7 Page - Dallas Semiconductor |
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7 / 21 page  DS80C310 031296 7/21 MEMORY ACCESS The DS80C310 contains no on–chip ROM, and 256 bytes of scratchpad RAM. Off–chip memory is accessed using the multiplexed address/data bus on P0 and the MSB address on P2. Timing diagrams are provided in the Electrical Specifications. Program memory (ROM) is accessed at a fixed rate determined by the crystal frequency and the actual instructions. As mentioned above, an instruction cycle requires four clocks. Data memory (RAM) is accessed according to a variable speed MOVX instruction as described below. STRETCH MEMORY CYCLE The DS80C310 allows the application software to adjust the speed of data memory access. The micro is capable of performing the MOVX in as few as two instruction cycles. However, this value can be stretched as needed so that both fast memory and slow memory or peripher- als can be accessed with no glue logic. Even in high– speed systems, it may not be necessary or desirable to perform data memory access at full speed. In addition, there are a variety of memory mapped peripherals such as LCD displays or UARTs that are not fast. The Stretch MOVX is controlled by the Clock Control Register at SFR location 8Eh as described below. This allows the user to select a stretch value between zero and seven. A Stretch of zero will result in a two machine cycle MOVX. A Stretch of seven will result in a MOVX of nine machine cycles. Software can dynamically change this value depending on the particular memory or peripheral. On reset, the Stretch value will default to a one resulting in a three cycle MOVX. Therefore, RAM access will not be performed at full speed. This is a convenience to existing designs that may not have fast RAM in place. When maximum speed is desired, the software should select a Stretch value of zero. When using very slow RAM or peripherals, a larger stretch value can be selected. Note that this affects data memory only and the only way to slow program memory (ROM) access is to use a slower crystal. Using a Stretch value between one and seven causes the microcontroller to stretch the read/write strobe and all related timing. This results in a wider read/write strobe allowing more time for memory/peripherals to respond. The timing of the variable speed MOVX is shown in the Electrical Specifications. Note that full speed access is not the reset default case. Table 3 shows the resulting strobe widths for each Stretch value. The memory stretch is implemented using the Clock Control Special Function Register at SFR loca- tion 8Eh. The stretch value is selected using bits CKCON.2–0. In the table, these bits are referred to as M2 through M0. The first stretch (default) allows the use of common 120 ns or 150 ns RAMs without dramatically lengthening the memory access. DATA MEMORY CYCLE STRETCH VALUES Table 3 CKCON.2–0 MEMORY CYCLES RD OR WR STROBE STROBE WIDTH TIME M2 M1 M0 MEMORY CYCLES RD OR WR STROBE WIDTH IN CLOCKS @ 25 MHz @ 33 MHz 0 0 0 2 2 80 ns 60 ns 0 0 1 3 (default) 4 160 ns 121 ns 0 1 0 4 8 320 ns 242 ns 0 1 1 5 12 480 ns 364 ns 1 0 0 6 16 640 ns 485 ns 1 0 1 7 20 800 ns 606 ns 1 1 0 8 24 960 ns 727 ns 1 1 1 9 28 1120 ns 848 ns |
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