ASAHI KASEI

[AK8973]

MS0561-E-01 <Preliminary>

- 17 -

2007/01

7.3.

READ Instruction

When the R/W bit is set to "1", AK8973 performs read operation.

If a master IC generates an acknowledge instead of a stop condition after AK8973 transfers the data at a

specified address, the data at the next address can be read.

If the reading of data starts from "C0H, C1H through C3H, C4H" or "E0H, E1H through E5H, E6H", and

additional data is read after reading, the internal address counter rolls over and the data at "C0H" or "E0H" is

read again.

AK8973 supports current address read and random read.

7.3.1.

Current Address READ

AK8973 has an address counter inside the LSI chip. In current address read operation, the data at an address

specified by this counter is read.

The internal address counter holds the next address of the most recently accessed address.

For example, if the address most recently accessed (for READ instruction) is address "n", and a current address

read operation is attempted, the data at address "n+1" is read.

In current address read operation, AK8973 generates an acknowledge after receiving a slave address for the

READ instruction (R/W bit="1"). Next, AK8973 transfers the data specified by the internal address counter

starting with the next clock pulse, then increments the internal counter by one. If the master IC generates a stop

condition instead of an acknowledge after AK8973 transmits one byte of data, the read operation stops.

SDA

S

T

A

R

T

A

C

K

A

C

K

S

Slave

Address

A

C

K

Data(n)

Data(n+1)

P

S

T

O

P

Data(n+x)

A

C

K

Data(n+2)

A

C

K

A

C

K

R/W="1"

Fig. 08 CURRENT ADDRESS READ

7.3.2.

Random READ

By random read operation, data at an arbitrary address can be read.

Random read operation requires to execute WRITE instruction as dummy before a slave address for the READ

instruction (R/W bit="1") is transmitted. In random read operation, a start condition is first generated then a

slave address for the WRITE instruction (R/W bit="0") and a read address are transmitted sequentially.

After AK8973 generates an acknowledge in response to this address transmission, a start condition and a slave

address for the READ instruction (R/W bit="1") are generated again. AK8973 generates an acknowledge in

response to this slave address transmission. Next, AK8973 transfers the data at the specified address then

increments the internal address counter by one. If the master IC generates a stop condition instead of an

acknowledge after data is transferred, the read operation stops.

SDA

S

T

A

R

T

A

C

K

A

C

K

S

Slave

Address

A

C

K

Register

Address(n)

Data(n)

P

S

T

O

P

Data(n+x)

A

C

K

Data(n+1)

A

C

K

A

C

K

R/W="0"

S

T

A

R

T

A

C

K

S

Slave

Address

R/W="1"

Fig. 09 RANDOM READ