ADS62P45 datasheet(15/67 Pages) TI

Part #	ADS62P45

Description	Dual Channel 14-Bit, 125/105/80/65 MSPS ADC with Parallel CMOS/DDR LVDS outputs

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Manufacturer	TI [Texas Instruments]

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ADS62P45, ADS62P44

ADS62P43, ADS62P42

REV1P0 SEP 2007

15

PRODUCT PREVIEW information concerns products in

the formative or design phase of development.

Characteristic data and other specifications are design

goals. Texas Instruments reserves the right to change or

discontinue these products without notice.

www.ti.com

ADS62P45

ADS62P44

ADS62P43

ADS62P42

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

PARALLEL CMOS INTERFACE, DRVDD = 2.5V TO 3.3V

tsu

Data setup time (5)

Data valid

(7)

to zero-

crossing of CLKOUT

TBD

3.5

TBD

4.3

TBD

5.8

TBD

7.2

ns

th

Data hold time (5)

Zero-crossing of

CLKOUT to data

becoming invalid

(7)

TBD

3.2

TBD

4

TBD

5.5

TBD

7

ns

tPDI

Clock propagation

delay

Input clock rising edge

cross-over to output

clock rising edge

cross-over

TBD

7.3

TBD

7.3

TBD

7.3

TBD

7.3

TBD

ns

Output clock duty

cycle

Duty cycle of output

clock, CLKOUT

53

tRISE, tFALL

Data rise time,

Data fall time

Rise time measured

from 20% to 80% of

DRVDD,

Fall time measured

from 80% to 20% of

DRVDD

1.5

ns

tCLKRISE, tCLKFALL

Output clock rise

time,

Output

clock fall time

Rise time measured

from 20% to 80% of

DRVDD

Fall time measured

from 80% to 20% of

DRVDD

1.5

ns

Notes:

1.

Timing parameters are ensured by design and characterization and not tested in production.

2.

CLOAD is the effective external single-ended load capacitance between each output pin and ground

3.

Io refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair.

4.

Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load.

5.

Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume that

the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as

reduced timing margin.

6.

Data valid refers to LOGIC HIGH of +100.0mV and LOGIC LOW of -100.0mV.

7.

Data valid refers to LOGIC HIGH of 2.0V and LOGIC LOW of 0.8V for DRVDD = 3.3V &

LOGIC HIGH of 1.7V and LOGIC LOW of 0.7V for DRVDD = 2.5V.

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