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ADS62P45 Datasheet(PDF) 1 Page - Texas Instruments

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Part # ADS62P45
Description  Dual Channel 14-Bit, 125/105/80/65 MSPS ADC with Parallel CMOS/DDR LVDS outputs
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADS62P45 Datasheet(HTML) 1 Page - Texas Instruments

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ADS62P45, ADS62P44
ADS62P43, ADS62P42
REV1P0 SEP 2007
1
Copyright
© 2007, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in
the formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
www.ti.com
www.ti.com
Dual Channel 14-Bit, 125/105/80/65 MSPS ADC with
Parallel CMOS/DDR LVDS outputs
FEATURES
§ Maximum Sample Rate: 125 MSPS
§ 14-bit Resolution with No Missing Codes
§ 92 dB Crosstalk at 50MHz
§ Parallel CMOS and DDR LVDS Output Options
§ 3.5 dB Coarse Gain and Programmable Fine
Gain up to 6 dB for SNR/SFDR trade-off
§ Supports Sine, LVPECL, LVDS & CMOS clock
inputs & amplitude down to 400 mV p-p
§ Digital Processing Block with
§ Offset correction
§ Fine gain correction, (0.05 dB step)
§ Decimation by 2/4/8
§ Built-in & Custom programmable 24-tap
Low / High / Band pass filters
§ Clock duty cycle stabilizer
§ Internal reference, supports external
reference also
§ 64-QFN Package (9mm x 9mm)
§ Pin compatible 12-bit family (ADS62P2X)
Table 1 ADS62PXX Dual Channel Family
125 MSPS
105 MSPS
80 MSPS
65 MSPS
14 bit
ADS62P45
ADS62P44
ADS62P43
ADS62P42
12 bit
ADS62P25
ADS62P24
ADS62P23
ADS62P22
11 bit
ADS62P15
-
-
-
Table 2 Performance Summary
ADS62P45
ADS62P44
ADS62P43
ADS62P42
Fin = 10 MHz
92
92
94
94
SFDR, dBc
Fin = 170 MHz, 3.5dB gain
81
82
83
84
Fin = 10 MHz
73.8
73.8
73.9
74
SINAD, dBFS
Fin = 170 MHz, 3.5dB gain
70.3
70.3
70.6
70.6
Power, mW per channel
396
350
294
259
DESCRIPTION
ADS62P4X is a family of dual channel 14-bit A/D converters with maximum sample rates up to 125 MSPS. It
combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample
and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has
coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.


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