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ADS62P45 Datasheet(PDF) 55 Page - Texas Instruments

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Part No. ADS62P45
Description  Dual Channel 14-Bit, 125/105/80/65 MSPS ADC with Parallel CMOS/DDR LVDS outputs
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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 55 page
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ADS62P45, ADS62P44
ADS62P43, ADS62P42
REV1P0 SEP 2007
55
PRODUCT PREVIEW information concerns products in
the formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
www.ti.com
www.ti.com
DETAILS OF THE DIGITAL PROCESSING BLOCK
OFFSET
ESTIMATION
BLOCK
24 TAP FILTER
- LOW PASS
- HIGH PASS
- BAND PASS
DECIMATION
BY 2/4/8
Disable offset
correction
Freeze offset
correction
0
Fine Gain
(0 to 6 dB
0.5 dB steps)
Gain Correction
(0.05 dB steps)
Bypass
decimation
Bypass filter
To output buffers
LVDS or CMOS
14 bits
14 bits
14 bits
14 bits
Filter Select
CLIPPER
DIGITAL PROCESSING BLOCK
OFFSET
CORRECTION
FINE GAIN
GAIN
CORRECTION
DIGITAL
FILTER & DECIMATION
From ADC
output
14 bits
14 bits
Figure 26 Digital Processing Block Diagram
Several common digital processing functions have been integrated in the device – offset correction, fine gain, gain correction
decimation & digital filters. By default after reset, the digital processing block is bypassed & all its functions are disabled.
OFFSET CORRECTION
ADS62P4X has an internal offset correction algorithm that estimates and corrects dc offset up to +/-10mV. The correction can
be enabled using the serial register bit <OFFSET LOOP EN>. Once enabled, the algorithm estimates the channel offset and
applies the correction every clock cycle. The time constant of the correction loop is a function of the sampling clock frequency.
The time constant can be controlled using register bits <OFFSET LOOP TC> as described in Table 9.
It is also possible to freeze the offset correction using the serial interface (<OFFSET LOOP FREEZE>). Once frozen, the offset
estimation becomes inactive and the last estimated value is used for correction every clock cycle. Note that the offset
correction is disabled by default after reset.
Figure 27 shows the time response of the offset correction algorithm, after it is enabled.




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