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ADS62P45 Datasheet(PDF) 50 Page - Texas Instruments

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Part No. ADS62P45
Description  Dual Channel 14-Bit, 125/105/80/65 MSPS ADC with Parallel CMOS/DDR LVDS outputs
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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ADS62P45, ADS62P44
ADS62P43, ADS62P42
REV1P0 SEP 2007
50
www.ti.com
www.ti.com
PRODUCT PREVIEW information concerns products in
the formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
Output Buffer Strength Programmability
Switching noise (caused by CMOS output data transitions) can couple into the analog inputs during the instant of sampling and
degrade the SNR. The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this,
ADS62P4X CMOS output buffers are designed with controlled drive strength to get best SNR. The default drive strength also
ensures wide data stable window for load capacitances up to 5 pF and DRVDD supply voltage > 2.2 V.
To ensure wide data stable window for load capacitance > 5 pF, there exists option to increase the output data & clock drive
strengths using the serial interface (<DATAOUT STRENGTH> & <CLKOUT STRENGTH>). Note that for DRVDD supply
voltage < 2.2 V, it is recommended to use maximum drive strength (for any value of load capacitance).
CMOS Interface Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every output pin. The
maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock cycle. In actual applications, this
condition is unlikely to occur. The actual DRVDD current would be determined by the average number of output bits switching,
which is a function of the sampling frequency and the nature of the analog input signal.
Digital current due to CMOS output switching = CL x DRVDD x (N x FAVG),
where CL = load capacitance, N x FAVG = average number of output bits switching.
Figure TBD shows the current with various load capacitances across sampling frequencies at 2 MHz analog input frequency.




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