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ADS62P45 Datasheet(PDF) 49 Page - Texas Instruments

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Part No. ADS62P45
Description  Dual Channel 14-Bit, 125/105/80/65 MSPS ADC with Parallel CMOS/DDR LVDS outputs
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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 49 page
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ADS62P45, ADS62P44
ADS62P43, ADS62P42
REV1P0 SEP 2007
49
PRODUCT PREVIEW information concerns products in
the formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
www.ti.com
www.ti.com
DIGITAL OUTPUT INFORMATION
ADS62P4X provides 14 bit data per channel and a common output clock synchronized with the data. The output interface can
be either parallel CMOS or DDR LVDS voltage levels and can be selected using serial register bit <OUTPUT INTERFACE> or
parallel pin SEN.
Parallel CMOS interface
In the CMOS mode, the output buffer supply (DRVDD) can be operated over a wide range from 1.8 V to 3.3 V (typical). Each
data bit is output on separate pin as CMOS voltage level, every clock cycle (Figure 20).
For DRVDD > 2.2 V, it is recommended to use the CMOS output clock (CLKOUT) to latch data in the receiving chip. The rising
edge of CLKOUT can be used to latch data in the receiver, even at the highest sampling speed. It is recommended to minimize
the load capacitance seen by data and clock output pins by using short traces to the receiver. Also, match the output data and
clock traces to minimize the skew between them.
For DRVDD < 2.2 V, it is recommended to use external clock (for example, input clock delayed to get desired setup / hold
times).
DA0
DA1
DA2
DA3
DA12
DA13
CLKOUT
CMOS
Output Buffers
14 bit Channel A
data
DB0
DB1
DB2
DB3
DB12
DB13
14 bit Channel B
Data
Figure 20 CMOS Output Interface




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