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ADS62P45 Datasheet(PDF) 48 Page - Texas Instruments

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Part No. ADS62P45
Description  Dual Channel 14-Bit, 125/105/80/65 MSPS ADC with Parallel CMOS/DDR LVDS outputs
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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 48 page
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ADS62P45, ADS62P44
ADS62P43, ADS62P42
REV1P0 SEP 2007
48
www.ti.com
www.ti.com
PRODUCT PREVIEW information concerns products in
the formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
POWER DOWN
ADS62P4X has three power down modes – power down global, channel standby and individual channel output buffer disable.
These can be set using either the serial register bits or using the control pins CTRL1 to CTRL3.
CONFIGURE USING
PARALLEL CONTROL PINS
POWER DOWN MODES
SERIAL INTERFACE
<POWER DOWN
MODES>
CTRL1
CTRL2
CTRL3
TOTAL
POWER,
mW (1)
WAKE-UP TIME
Normal operation
000
low
low
low
792
-
Channel A output buffer disabled
001
low
low
high
782
Fast (100 ns)
Channel B output buffer disabled
010
low
high
low
782
Fast (100 ns)
Channel A & B output buffer disabled
011
low
high
high
772
Fast (100 ns)
Power down global
100
high
low
low
50
Slow (15 μs)
Channel A standby
101
high
low
high
482
Fast (100 ns)
Channel B standby
110
high
high
low
482
Fast (100 ns)
Multiplexed (MUX) mode – Output data of
channel A & B is multiplexed & available on
DB13 to DB0 pins.
111
high
high
high
-
-
1.
Sampling frequency = 125 MSPS, DRVDD = 1.8V
Power down global
In this mode, the entire chip including both the A/D converters, internal reference and the output buffers are powered down
resulting in reduced total power dissipation of about 50 mW. The output buffers are in high impedance state. The wake-up time
from the global power down to data becoming valid in normal mode is typically 15 μ s.
Channel standby (individual or both channels)
This mode allows the individual ADCs to be powered down. The internal references are active & this results in fast wake-up
time, about 100 ns. The total power dissipation in standby is about 482 mW.
Output buffer disable (individual or both channels)
Each channel’ s output buffer can be disabled & put in high impedance state
. Wakeup time is fast, about 100 ns.
Input clock stop
In addition to the above, the converter enters a low-power mode when the input clock frequency falls below 1 MSPS. The
power dissipation is about 140 mW.
POWER SUPPLY SEQUENCE
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are separated in the
device. Externally, they can be driven from separate supplies or from a single supply.




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