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TMS28F002MB80CDBJQ Datasheet(PDF) 6 Page - Texas Instruments |
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TMS28F002MB80CDBJQ Datasheet(HTML) 6 Page - Texas Instruments |
6 / 79 page TMS28F002Axy, TMS28F200Axy 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 functional block diagram Counter Address Address Latch Control Reduction Power- X Decoder Y Decoder Y Gating / Sensing Block Main 128K-Byte Block Main 96K-Byte Block Parameter 8K-Byte Block Parameter 8K-Byte Block Boot 16K-Byte I/O Logic Program/ Voltage Switch Erase Machine State Write - Data Comparator Register Data Input Buffer Input Buffer Register Status Register Identification Multiplexer Output Input Buffer DQ15/A –1 Output Buffer Buffer Output DQ8 – DQ15/A –1† DQ0 – DQ7 A0 – A16 BYTE† E W G RP VPP Input Buffer 17 8 8 8 WP Machine State Command - † Not used on ’F002 model architecture The TMS28F200Axy uses a blocked architecture to allow independent erasure of selected memory blocks. The block to be erased is selected by using any valid address within that block. block-memory maps The TMS28F200Axy is available with the block architecture mapped in either of two configurations: the boot block located at the top or at the bottom of the memory array, as required by different microprocessors. The TMS28F200AxB (bottom boot block ) is mapped with the 16K-byte boot block located at the low-order address range (00000h to 01FFFh). The TMS28F200AxT (top boot block ) is inverted with respect to the TMS28F200AxB with the boot block located at the high-order address range (1E000h to 1FFFFh). Both of these address ranges are for word-wide mode. The TMS28F002Axy is mapped as the 8-bit configuration of the TMS28F200Axy, except that the least signficant bit (LSB) is A0 instead of A–1. Figure 1 and Figure 2 show the memory maps for these configurations. |
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