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MAX6356 Datasheet(PDF) 8 Page - Maxim Integrated Products

Part No. MAX6356
Description  Dual/Triple-Voltage μP Supervisory Circuits
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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MAX6356 Datasheet(HTML) 8 Page - Maxim Integrated Products

 
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Dual/Triple-Voltage
µP Supervisory Circuits
8
_______________________________________________________________________________________
During the normal operating mode, the supervisor will
issue a reset pulse for the reset timeout period (140ms
min) if the µP does not update the WDI with a valid tran-
sition (HIGH to LOW or LOW to HIGH) within the stan-
dard timeout period (1.6s min).
After each reset event (VCC power-up, manual reset, or
watchdog reset), there is an initial watchdog startup
timeout period of 25.6s. The startup mode provides an
extended period for the system to power up and fully
initialize all µP and system components before assum-
ing responsibility for routine watchdog updates. The
normal watchdog timeout period (1.6s min) begins at
the conclusion of the startup timeout period or after the
first transition on WDI before the conclusion of the start-
up period (Figure 3).
Applications Information
Ensuring a Valid
RESET Output
Down to VCC = 0
In some systems, it is necessary to ensure a valid reset
even if VCC falls to 0. In these applications, use the cir-
cuit shown in Figure 4. Note that this configuration does
not work for the open-drain outputs of the MAX6352/
MAX6355/MAX6358.
Interfacing to µPs with
Bidirectional Reset Pins
Microprocessors with bidirectional reset pins will con-
tend with the push-pull outputs of these devices. To
prevent this, connect a 4.7k
Ω resistor between RESET
and the µP’s reset I/O port, as shown in Figure 5. Buffer
RESET as shown in the figure if this reset is used by
other components in the system.
Figure 4. Ensuring a Valid Reset Low to VCC1 and VCC2 = 0
VCC2VCC1
GND
100k
RST2
RST1
RST
MAX6351 MAX6356
MAX6353 MAX6357
MAX6354 MAX6359
MAX6360
VCC2
VCC1
Figure 5. Interfacing to µPs with Bidirectional Reset I/O
BUFFERED RESET TO OTHER SYSTEM COMPONENTS
4.7k
GND
RESET
µP
GND
RST2
RST1
RST
MAX6351–MAX6360
VCC2
VCC2
VCC1
VCC1
1.6s
MAX
tWDI-NORMAL
1.6s MAX
tWDI-STARTUP
25.6s MAX
VTH
VCC
WDI
RESET
140ms
Figure 3. Normal Watchdog Startup Sequence
Chip Information
TRANSISTOR COUNT: 855


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