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ICS9DB202CGL Datasheet(PDF) 8 Page - Integrated Device Technology |
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ICS9DB202CGL Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 13 page IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 8 ICS9DB202CG REV B JULY 14, 2006 ICS9DB202 PCI EXPRESS JITTER ATTENUATOR FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVDS DRIVER 3.3V R1 50 R3 50 Zo = 50 Ohm LVPECL Zo = 50 Ohm HiPerClockS CLK nCLK 3.3V Input R2 50 Zo = 50 Ohm Input HiPerClockS CLK nCLK 3.3V R3 125 R2 84 Zo = 50 Ohm 3.3V R4 125 LVPECL R1 84 3.3V DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING and VOH must meet the V PP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY ICS HIPERCLOCKS LVHSTL DRIVER examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 1.8V R2 50 Input LVHSTL Driver ICS HiPerClockS R1 50 LVHSTL 3.3V Zo = 50 Ohm Zo = 50 Ohm HiPerClockS CLK nCLK Zo = 50 Ohm R1 100 3.3V LVDS_Driv er Zo = 50 Ohm Receiv er CLK nCLK 3.3V INPUTS: LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kW resistor can be used. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: HCSL OUTPUT All unused HCSL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. |
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