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74VHCT74A Datasheet(PDF) 1 Page - STMicroelectronics

Part No. 74VHCT74A
Description  DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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74VHCT74A Datasheet(HTML) 1 Page - STMicroelectronics

 
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74VHCT74A
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
March 2000
s
HIGH SPEED:
fMAX =160 MHz (TYP.) at VCC =5V
s
LOW POWER DISSIPATION:
ICC =2
µA (MAX.) at TA =25 oC
s
COMPATIBLE WITH TTL OUTPUTS:
VIH =2V (MIN), VIL = 0.8V (MAX)
s
POWER DOWN PROTECTION ON INPUTS &
OUTPUTS
s
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|=IOL = 8 mA (MIN)
s
BALANCED PROPAGATION DELAYS:
tPLH
≅ tPHL
s
OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74VHCT74A is an advanced high-speed
CMOS
DUAL
D-TYPE
FLIP
FLOP
WITH
PRESET AND CLEAR fabricated with sub-micron
silicon gate and double-layer metal wiring C
2MOS
technology.
A signal on the D INPUT is transfered to the Q
OUTPUT during the positive going transition of
the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
All inputs
and
outputs are
equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
®
SOP
TSSOP
ORDER CODES
PACKAGE
T UBE
T & R
SOP
74VHCT74AM
74VHCT74AMTR
TSSOP
74VHCT74ATTR
1/10


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