IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
2/111
Mar 09, 2007
Copyright © 2004, IC Plus Corp.
IP175C/IP175CH-DS-R14
Table Of Contents
Features................................................................................................................................................... 1
General Description................................................................................................................................. 1
Table Of Contents .................................................................................................................................... 2
Revision History....................................................................................................................................... 4
Comparison Table of IP175A & IP175C/IP175CH................................................................................... 6
Pin diagram (IP175C) .............................................................................................................................. 7
Pin diagram (IP175CH) ........................................................................................................................... 8
1
Pin description................................................................................................................................12
2
Functional Description.................................................................................................................... 34
2.1
Flow control........................................................................................................................ 34
2.2
Broadcast storm protection ................................................................................................ 34
2.3
Port locking (Port security)................................................................................................. 34
2.4
Port base VLAN ................................................................................................................. 34
2.5
Tag VLAN / Tag and un-tag function .................................................................................. 35
2.5.1
Tag and un-tag function ........................................................................................ 35
2.5.2
Tag VLAN .............................................................................................................. 35
2.5.3
Tag/ un-tag function and Tag VLAN function in a router application..................... 35
2.6
MII/RMII.............................................................................................................................. 36
2.7
SMART MAC...................................................................................................................... 42
2.7.1
System configuration ............................................................................................ 42
2.7.2
Packet from LAN to WAN ..................................................................................... 44
2.7.3
Packet from WAN to LAN ..................................................................................... 44
2.8
Built in regulator ................................................................................................................. 45
2.9
CoS .................................................................................................................................... 46
2.9.1
Port base priority................................................................................................... 46
2.9.2
Frame base priority ............................................................................................... 46
2.10
Spanning tree ..................................................................................................................... 48
2.10.1
Port states ............................................................................................................. 48
2.11
Special tag.......................................................................................................................... 49
2.11.1
From CPU to switch .............................................................................................. 49
2.11.2
From switch to CPU .............................................................................................. 49
U
2.12
Static MAC address table................................................................................................... 50
2.13
Serial mode LED ................................................................................................................ 51
2.14
LED Blink Timing................................................................................................................ 53
2.15
Serial management interface ............................................................................................. 54
2.16
Force mode of PHY ........................................................................................................... 56
2.17
Reset.................................................................................................................................. 56
2.18
Bandwidth control............................................................................................................... 56
2.19
Fiber mode of port 4 (for IP175CH only)............................................................................ 56
2.20
MII registers of PHY........................................................................................................... 58
2.21
MII registers of Switch controller........................................................................................ 66
3
Electrical Characteristics .............................................................................................................. 101
3.1
Absolute Maximum Rating ............................................................................................... 101
3.2
DC Characteristic ............................................................................................................. 101
3.3
AC Timing......................................................................................................................... 102
3.3.1
Reset Timing ....................................................................................................... 102
3.3.2
PHY Mode MII Timing ......................................................................................... 102
3.3.3
MAC Mode MII Timing ........................................................................................ 104
3.3.4
RMII Timing ......................................................................................................... 105
3.3.5
SNI Timing .......................................................................................................... 106
3.3.6
SMI Timing .......................................................................................................... 107
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