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IP1726LF-DS-R06 Datasheet(PDF) 11 Page - List of Unclassifed Manufacturers

Part # IP1726LF-DS-R06
Description  26-port 10/100M Smart Switch Controller
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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IP1726LF-DS-R06 Datasheet(HTML) 11 Page - List of Unclassifed Manufacturers

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IP1726 LF
Preliminary Data Sheet
11/33
Jun 15, 2005
Copyright © 2003, IC Plus Corp.
IP1726 LF-DS-R06
4
Functional Description
4.1
Medium Access Control(MAC)
4.1.1 Data Rate Control
The IP1726 LF implements a sophisticated data rate control mechanism, which is very useful for the
bandwidth-limited network. By controlling both the ingress data rate and the egress data rate, the IP1726
LF provides a variety of the bandwidth configuration.
By means of calculating the maximum TX/RX byte number in a time unit of the corresponding port, the
IP1726 LF provides a precise bandwidth control mechanism. The formula for calculating the maximum
byte during a time unit is:
M.B.N= S.D.R* 512
Where M.B.N stands for the maximum byte number;
S.D.R the specified data rate.
The time unit is 10ms at 100 Mbps speed and 100ms at 10Mbps speed.
The data rate for each port is specified in registers ranging from 03H to 1CH.
If the transmit/receive byte number reaches the specified M.B.N after the transmit/receive timer expires,
the MAC will continue the operation until the whole data packet is transmitted/received and then wait until
the next time unit starts.
For example, if the value set to register 06H is 12H(18 in decimal) and the port 1 runs at 100Mbps speed,
the maximum byte number allowed to transmit through port 1 is 9216 bytes(the result of 512*18) within
10ms( 1,000,000 bit time). 9216 bytes stands for 73,728 bit time. The flow control mechanism will be
activated for the spare time. Thus the data rate can be limited to a specified value.
4.1.2 Flow Control
The IP1726 LF embeds the flow control mechanism for both full duplex mode and half duplex mode. When
the buffer reach a pre-defined level, the transmit MAC will generate the flow control pattern to prevent the
buffer overflow. These flow control patterns are dependent on the duplex mode. The IP1726 LF transmit
MAC generates the backpressure pattern in half duplex mode and the 802.3x pause packet in full duplex
mode.
When operating in half duplex mode, the IP1726 LF should comply with CSMA/CD standard. The
transmit MAC will generate the jam pattern to inform the link partner that the receive buffer is not
available when the buffer reaches a pre-defined level. The IP1726 LF supports the collision_based
backpressure. When the collision_based backpressure is enabled, the transmit MAC of the IP1726 LF
will generate the jam pattern only when the link partner is transmitting data and the buffer is not available.
When detecting the collision on line, the link partner will back off the transmission and then wait until the
back off time expires.
The IP1726 LF uses 802.3x pause packet to accomplish the flow control for full duplex mode. When the
buffer reach a pre-defined level, the transmit MAC generates a Xoff pause packet immediately or right
after the current packet has been transmitted. When receiving a pause packet, the link partner will stop
the transmission for a time period according to the pause value carried by the pause packet, preventing
the internal buffer from overrun.


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