6 / 33 page IP1718 LF Preliminary Data Sheet 6/33 January 27, 2005 Copyright © 2003, IC Plus Corp. IP1718 LF-DS-R05 3 Pin description Type Description P Positive power or ground I; O I: Input pin; O:Output pin IL Input latched upon reset Type Description PD, PD:Pulled down with internal resistor PU PU:Pulled up with internal resistor I/O Bi-direction Input/Output Pin No. Label Type Description SS-SMII 117, 119 121, 123, 128, 7, 9, 11, 15, 17, 19, 21, 28, 31, 33, 35, P1TXD, P2TXD, P3TXD, P4TXD, P5TXD, P6TXD, P7TXD, P8TXD, P9TXD, P10TXD, P11TXD, P12TXD, P13TXD, P14TXD, P15TXD, P16TXD, O SS-SMII transmit data output for port 1 to port 16. 126, 26, TXSYNC1, TXSYNC2, O SS-SMII synchronization output for transmit data 127, 27, TXCLK1, TXCLK2, O SS-SMII transmit clock output 118, 120, 122, 124, 6, 8, 10, 12, 16, 18, 20, 22, 30, 32, 34, 36, P1RXD, P2RXD, P3RXD, P4RXD, P5RXD, P6RXD, P7RXD, P8RXD, P9RXD, P10RXD, P11RXD, P12RXD, P13RXD, P14RXD, P15RXD, P16RXD, I SS-SMII receive data input 42, 44, 46, 48, 56, 60, 62, 64 49, 55 GND I Should be tied to GND. 125, 25, RXSYNC1, RXSYNC2, I SS-SMII receive synchronization input 5, 29, RXCLK1, RXCLK2, I SS-SMII receive clock input |
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