IP1718 LF
Preliminary Data Sheet
7/33
January 27, 2005
Copyright © 2003, IC Plus Corp.
IP1718 LF-DS-R05
Pin description
(continued)
Pin No.
Label
Type
Description
MII/Reverse MII
95
M1TXEN
O
1st MII (port 17) transmit enable
94, 93, 92, 91
M1TXD[3:0]
O
1st MII (port 17) transmit data output
84
M1RXDV
I
1st MII (port 17) receive valid
88, 87, 86, 85
M1RXD[3:0]
I
1st MII (port 17) receive data input
90
M1TXC
I/O
1st MII (port 17) transmit clock. Input for normal (MAC
mode) MII. Output for reverse (PHY mode) MII
89
M1RXC
I/O
1st MII (port 17) receive clock. Input for normal (MAC
mode) MII. Output for reverse (PHY mode) MII.
111
M2TXEN
O
2nd MII (port 18) transmit enable
110,109,108,1
07
M2TXD[3:0]
O
2nd MII (port 18) transmit data output
98
M2RXDV
I
2nd MII (port 18) receive valid
104,103,100,9
9
M2RXD[3:0]
I
2nd MII (port 18) receive data input
106
M2TXC
I/O
2nd MII (port 18) transmit clock. Input for normal (MAC
mode) MII. Output for reverse (PHY mode) MII
105
M2RXC
I/O
2nd MII (port 18) receive clock. Input for normal (MAC
mode) MII. Output for reverse (PHY mode) MII.
112
M2COL
I/O
2nd MII (port 18) collision input. Input for normal MII
Output for reverse MII
13
MDC
O
Clock for serial management bus. It’s recommended to
add a 30pf capacitor to ground for noise filetrring.
14
MDIO
I/O
I/O data for serial manment bus. It’s recommended to
add a 4.7K pull up resistor connecting to VDD and a
30pf capacitor connecting to ground.
Miscellaneous
70
X1/OSCI
I
Crystal/ Oscillator 25MHz input
71
X2
O
Crystal output
72
RESETB
I
System reset (low active). Should be kept at “low” for at
least 10 microseconds.
97
CLK25M
O
This output pin is 25MHz clock signal which is the
counterpart of the clock generated by the X’tal placed
on X1 & X2.
75
SCL
O, PU Serial EEPROM clock output
76
SDA
I/O,PU Serial EEPROM data
78
SCPUC
I, PU
Serial CPU access clock input. Please see the section
of “Programming the Internal Register” for the usage of
SCPUC and SCPUIO.
79
SCPUIO
I/O,
PU
Serial CPU data
77
INTB
O, PU Interrupt output. Active low.
74
TEST
O, PD Test mode control.
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