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SNJ54LV139AFK Datasheet(PDF) 2 Page - Texas Instruments |
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SNJ54LV139AFK Datasheet(HTML) 2 Page - Texas Instruments |
2 / 19 page SN54LV139A, SN74LV139A DUAL 2LINE TO 4LINE DECODERS/DEMULTIPLEXERS SCLS396I − APRIL 1998 − REVISED APRIL 2005 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) These devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The ’LV139A devices comprise two individual 2-line to 4-line decoders in a single package. The active-low enable (G) input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. FUNCTION TABLE INPUTS OUTPUTS G SELECT OUTPUTS G B A Y0 Y1 Y2 Y3 H X X H H H H L L LL HH H L L HH LH H L H LH HLH L H H H H H L |
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