X25160

3

PRINCIPLES OF OPERATION

directly with the synchronous serial peripheral interface

(SPI) of many popular microcontroller families.

The X25160 contains an 8-bit instruction register. It is

accessed via the SI input, with data being clocked in on

the rising SCK.

CS must be LOW and the HOLD and WP

inputs must be HIGH during the entire operation. The

WP input is “Don’t Care” if WPEN is set “0”.

Table 1 contains a list of the instructions and their

opcodes. All instructions, addresses and data are trans-

ferred MSB first.

Data input is sampled on the first rising edge of SCK after

CS goes LOW. SCK is static, allowing the user to stop

the clock and then resume operations. If the clock line is

shared with other peripheral devices on the SPI bus, the

user can assert the

HOLD input to place the X25160 into

a “PAUSE” condition. After releasing

HOLD, the X25160

will resume operation from the point when

HOLD was

first asserted.

Write Enable Latch

The X25160 contains a “write enable” latch. This latch

must be SET before a write operation will be completed

internally. The WREN instruction will set the latch and

the WRDI instruction will reset the latch. This latch is

automatically reset upon a power-up condition and after

the completion of a byte, page, or status register write

cycle.

Status Register

The RDSR instruction provides access to the status

register. The status register may be read at any time,

even during a write cycle. The status register is format-

ted as follows:

WPEN, BP0 and BP1 are set by the WRSR instruction.

WEL and WIP are read-only and automatically set by

other operations.

The Write-In-Process (WIP) bit indicates whether the

X25160 is busy with a write operation. When set to a “1”,

a write is in progress, when set to a “0”, no write is in

progress. During a write, all other bits are set to “1”.

The Write Enable Latch (WEL) bit indicates the status of

the “write enable” latch. When set to a “1”, the latch is set,

when set to a “0”, the latch is reset.

The Block Protect (BP0 and BP1) bits are nonvolatile

and allow the user to select one of four levels of protec-

tion. The X25160 is divided into four 4096-bit segments.

One, two, or all four of the segments may be protected.

That is, the user may read the segments but will be

unable to alter (write) data within the selected segments.

The partitioning is controlled as illustrated below.

Status Register Bits

Array Addresses

BP1

BP0

Protected

0

0

None

0

1

$0600–$07FF

1

0

$0400–$07FF

1

1

$0000–$07FF

3064 PGM T03

Table 1. Instruction Set

Instruction Name

Instruction Format*

Operation

WREN

0000 0110

Set the Write Enable Latch (Enable Write Operations)

WRDI

0000 0100

Reset the Write Enable Latch (Disable Write Operations)

RDSR

0000 0101

Read Status Register

WRSR

0000 0001

Write Status Register

READ

0000 0011

Read Data from Memory Array beginning at selected

address

WRITE

0000 0010

Write Data to Memory Array beginning at Selected Address

(1 to 32 Bytes)

3064 PGM T04

*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

7

654

3

2

1

0

WPEN

X

X

X

BP1

BP0

WEL

WIP

3064 PGM T02