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X25040 Datasheet(PDF) 1 Page - IC MICROSYSTEMS

Part No. X25040
Description  SPI Serial E2PROM with Block LockTM Protection
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Maker  ICMIC [IC MICROSYSTEMS]
Homepage  http://www.icmic.com
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X25040 Datasheet(HTML) 1 Page - IC MICROSYSTEMS

 
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This X25040 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
1
4K
X25040
512 x 8 Bit
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
Characteristics subject to change without notice
6451-3.6 6/10/96 T5/C1/D0 NS
Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc.
FEATURES
1MHz Clock Rate
SPI Modes (0,0 & 1,1)
512 X 8 Bits
4 Byte Page Mode
Low Power CMOS
—150
µA Standby Current
—3mA Active Current
2.7V To 5.5V Power Supply
Block Lock Protection
Protect 1/4, 1/2 or all of E
2PROM Array
Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Latch
Write Protect Pin
Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
High Reliability
—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years
ESD protection: 2000V on all pins
8-Lead PDlP Package
8-Lead SOIC Package
DESCRIPTION
The X25040 is a CMOS 4096-bit serial E
2
PROM, internally
organized as 512 x 8. The X25040 features a Serial
Peripheral Interface (SPI) and software protocol allowing
operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI) and
data out (SO) lines. Access to the device is controlled
through a chip select (CS) input, allowing any number of
devices to share the same bus.
The X25040 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25040 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The WP input can be used as a hardwire input to
the X25040 disabling all write attempts, thus providing
a mechanism for limiting end user capability of altering the
memory.
The X25040 utilizes Xicor’s proprietary Direct Write™ cell,
providing a minimum endurance of 100,000 cycles
per byte and a minimum data retention of 100 years.
COMMAND
DECODE
AND
CONTROL
LOGIC
WRITE
CONTROL
AND
TIMING
LOGIC
WRITE
PROTECT
LOGIC
X DECODE
LOGIC
512 BYTE
ARRAY
32 X 32
Y DECODE
DATA REGISTER
32 X 32
64 X 32
SO
SI
SCK
CS
HOLD
WP
32
32
64
8
4
STATUS
REGISTER
6451 FHD F01
FUNCTIONAL DIAGRAM
SPI Serial E
2PROM with Block LockTM Protection
ICmic
IC MICROSYSTEMS
TM


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