Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

X24645 Datasheet(PDF) 5 Page - IC MICROSYSTEMS

Part No. X24645
Description  Advanced 2-Wire Serial E2PROM with Block LockTM Protection
Download  18 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  ICMIC [IC MICROSYSTEMS]
Homepage  http://www.icmic.com
Logo 

X24645 Datasheet(HTML) 5 Page - IC MICROSYSTEMS

 
Zoom Inzoom in Zoom Outzoom out
 5 / 18 page
background image
X24645
5
Figure 5. Byte Write
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24645
S
T
A
R
T
SLAVE
ADDRESS
S
S
T
O
P
P
A
C
K
A
C
K
A
C
K
BYTE
ADDRESS
DATA
2783 ILL F08.1
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing (see Figure 4). The
next two bits are the device select bits. A system could have
up to four X24645’s on the bus. The four
addresses are defined by the state of the S1 and S2 inputs.
S2 of the slave address must be the inverse of
the S2 input pin.
Figure 4. Slave Address
The next five bits of the slave address are an extension of
the array’s address and are concatenated with
the eight bits of address in the byte address field,
providing direct access to the whole 8192 x 8 array.
2783 ILL F07.1
S
2
A9
A8
R/W
DEVICE
SELECT
S
1
A12
HIGH ORDER
ADDRESS
BITS
A11 A10
The last bit of the slave address defines the operation to be
performed. When set HIGH a read operation is
selected, when set LOW, a write operation is selected.
Following the start condition, the X24645 monitors the SDA
bus comparing the slave address being transmitted
with its slave address device type identifier. Upon a
correct compare the X24645 outputs an acknowledge on
the SDA line. Depending on the state of the R/W bit, the
X24645 will execute a read or write operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24645 requires a second ad-
dress field. This address field is the byte address, com-
prised of eight bits, providing access to any one of 8192
words in the array. Upon receipt of the byte address, the
X24645 responds with an acknowledge and awaits the
next eight bits of data, again responding with an acknowledge
The master then terminates the transfer by generating a
stop condition, at which time the X24645 begins
the internal write cycle to the nonvolatile memory. While the
internal write cycle is in progress the X24645 inputs
are disabled, and the device will not respond to any requests
from the master. Refer to Figure 5 for the address,
acknowledge and data transfer sequence.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn