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X24165 Datasheet(PDF) 5 Page - IC MICROSYSTEMS

Part No. X24165
Description  Advanced 2-Wire Serial E2PROM with Block LockTM Protection
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Maker  ICMIC [IC MICROSYSTEMS]
Homepage  http://www.icmic.com
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X24165 Datasheet(HTML) 5 Page - IC MICROSYSTEMS

 
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X24165
5
Figure 5. Byte Write
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24165
S
T
A
R
T
SLAVE
ADDRESS
S
S
T
O
P
P
A
C
K
A
C
K
A
C
K
WORD
ADDRESS
DATA
6551 ILL F08
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing (see Figure 4). The
next three bits are the device select bits. A system could
have up to eight X24165’s on the bus. The eight
addresses are defined by the state of the S0, S1 and S2
inputs. S1 of the slave address must be the inverse
of the S1 input pin.
Figure 4. Slave Address
The next three bits of the slave address are an extension
of the array’s address and are concatenated with
the eight bits of address in the word address field,
providing direct access to the whole 2048 x 8 array.
6551 ILL F07.2
1
A9
A8
R/W
DEVICE
SELECT
S
2
S
1
HIGH ORDER
WORD
ADDRESS
S
0
A10
DEVICE
TYPE
IDENTIFIER
The last bit of the slave address defines the operation to be
performed. When set HIGH a read operation is
selected, when set LOW a write operation is selected.
Following the start condition, the X24165 monitors the SDA
bus comparing the slave address being transmitted
with its slave address device type identifier. Upon a
correct compare the X24165 outputs an acknowledge on
the SDA line. Depending on the state of the R/W bit, the
X24165 will execute a read or write operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24165 requires a second ad-
dress field. This address field is the word address, com-
prised of eight bits, providing access to any one of 2048
words in the array. Upon receipt of the word address, the
X24165 responds with an acknowledge and awaits the
next eight bits of data, again responding with an acknowledge
The master then terminates the transfer by generating a
stop condition, at which time the X24165 begins
the internal write cycle to the nonvolatile memory. While
the internal write cycle is in progress the X24165 inputs
are disabled, and the device will not respond to any requests
from the master. Refer to Figure 5 for the address,
acknowledge and data transfer sequence.


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