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X76F102 Datasheet(PDF) 9 Page - IC MICROSYSTEMS

Part # X76F102
Description  Secure SerialFlash
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Manufacturer  ICMIC [IC MICROSYSTEMS]
Direct Link  http://www.icmic.com
Logo ICMIC - IC MICROSYSTEMS

X76F102 Datasheet(HTML) 9 Page - IC MICROSYSTEMS

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X76F102
9
AC CHARACTERISTICS
(TA = -40˚C to +85˚C, VCC = +3.0V to +5.5V, unless otherwise specified.)
Notes: 1.
Cb = total capacitance of one bus line in pF
2.
tAA = 1.1µs Max below VCC = 3.0V.
RESET AC SPECIFICATIONS
Power Up Timing
Notes: 1.
Delays are measured from the time VCC is stable until the specified operation can be initiated.These parameters are periodically sampled
and not 100% tested.
2.
Typical values are for TA = 25˚C and VCC = 5.0V
Nonvolatile Write Cycle Timing
Notes: 1.
tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Symbol
Parameter
Min
Max
Units
fSCL
SCL Clock Frequency
0
1
MHz
tAA(2)
SCL LOW to SDA Data Out Valid
0.1
0.9
µs
tBUF
Time the Bus Must Be Free Before a New Transmission Can
Start
1.2
µs
tHD:STA
Start Condition Hold Time
0.6
µs
tLOW
Clock LOW Period
1.2
µs
tHIGH
Clock HIGH Period
0.6
µs
tSU:STA
Start Condition Setup Time (for a Repeated Start Condition)
0.6
µs
tHD:DAT
Data In Hold Time
10
ns
tSU:DAT
Data In Setup Time
100
ns
tR
SDA and SCL Rise Time
20+0.1XCb
(1)
300
ns
tF
SDA and SCL Fall Time
20+0.1XCb
(1)
300
ns
tSU:STO
Stop Condition Setup Time
0.6
µs
tDH
Data Out Hold Time
0
µs
tNOL
RST to SCL Non-Overlap
500
ns
tRDV
RST LOW to SDA Valid During Response to Reset
0
450
ns
tCDV
CLK LOW to SDA Valid During Response to Reset
0
450
ns
tRST
RST High Time
1.5
µs
tSU:RST
RST Setup Time
500
ns
Symbol
Parameter
Min.
Typ(2)
Max.
Units
tPUR
(1)
Time from Power Up to Read
1
mS
tPUW
(1)
Time from Power Up to Write
5
mS
Symbol
Parameter
Min.
Typ.(1)
Max.
Units
tWC
(1)
Write Cycle Time
5
10
mS


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