ICM7563/7543/7523

Rev. A7

ICmic reserves the right to change specifications without prior notice

7

DETAILED DESCRIPTION

The ICM7563 is a 12-bit voltage output Quad DAC. The ICM7543 is the 10-bit version of this family and the ICM7523 is the 8-bit

version. These devices have a 16-bit input shift register and each DAC has a double buffered input.

This family of DACs has a guaranteed monotonic behavior. The operating supply range is from 2.7V to 5.5V.

Reference Input

The reference input accepts positive DC and AC signals. The voltage at REFIN sets the full-scale output voltage of all the DACs.

The reference input voltage range is from 0 to VDD-1.5V. The impedance at this pin is very high (greater than 10 M Ohm). Each

To determine the output voltage for any code, use the following equation.

ICM7563, 10 for ICM7543 and 8 for ICM7523.

Output Buffer Amplifier

The Quad DAC has 4 output amplifiers connected in a gain of 2 configuration. These amplifiers have a wide output voltage swing.

The actual swing of the output amplifiers will be limited by offset error and gain error. See the Applications Information Section for

a more detailed discussion.

The output amplifier can drive a load of 2.0 K

The output amplifier has a full-scale typical settling time of 8 s and it dissipates about 100 A with a 3V supply voltage.

Serial Interface and Input Logic

This quad DAC family uses a standard 3-wire connection compatible with SPI/QSPI and Microwire interfaces. Data is always

loaded in 16-bit words which consist of 4 address and control bits (MSBs) followed by 12 bits (see Figure .3). The last 5 bits of

this 12 bit word are also used for power down control (see tables 1 and 2). Each DAC is double buffered with an input latch and

DAC latch.

Serial Data Input

SDI (Serial Data Input) pin is the data input pin for all DACs. Data is clocked in on the falling edge of SCK which has a Schmitt

trigger internally to allow for noise immunity on the SCK pin. This specially eases the use for opto-coupled interfaces.

pulse the data is automatically transferred to a 16-bit input latch and the 4 bit control word (C3~C0) is then decoded and the

appropriate DAC is updated or loaded depending on the control word (see Table 1). Chip Select pin must be pulled high (level-

triggered) and back low for the next data word to be loaded in. This pin also disables the SCK pin internally when pulled high.

The DAC has a double-buffered input with an input latch and a DAC latch. The DAC output will swing to its new value when data

is loaded into the DAC latch. The user has three options: loading only the input latch, updating the DAC with data previously

loaded into the input latch or loading the input latch and updating the DAC at the same time with a new code. The actual data that

gets loaded into the DAC latch is D11~D0 for the ICM7563, D9~D0 for the ICM7543 and D7~D0 for the ICM 7523.

Power-Down Mode

The DAC have three Software-Selectable Power-Down Output Impedances (1 K Ohm, 100 K Ohm and Hi-Z) as additional safety

feature for applications that drive transducers or valves. The power down can be done with loading the control word with 1111 (C0

to C3). Tthe selection of the Output Impedance of DAC is controlled by the last 5 bits. See Table 1 and Table 2 for details of

operation of this function.

Power-On Reset

There is a power-on reset on board that will clear the contents of all the latches to all 0s on power-up and the DAC voltage output

will go to ground.

APPLICATIONS INFORMATION