 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SII3114CTU Datasheet(PDF) 11 Page - Silicon image |
|
||||||||||||||||||||||||||||||
SII3114CTU Datasheet(HTML) 11 Page - Silicon image |
|
|
11 / 127 page  SiI3114 PCI to Serial ATA Controller Data Sheet Silicon Image, Inc. © 2007 Silicon Image, Inc. 3 SiI-DS-0103-D • Configuration Read • Configuration Write • Memory Read • Memory Write All other PCI cycles are ignored by the SiI3114. As a PCI master, the SiI3114 generates the following PCI bus operations: • Memory Read Multiple • Memory Read • Memory Write PCI Configuration Space This section describes how the SiI3114 implements the required PCI configuration register space. The intent of PCI configuration space definition is to provide an appropriate set of configuration registers that satisfy the needs of current and anticipated system configuration mechanisms, without specifying those mechanisms or otherwise placing constraints on their use. These registers allow for: • Full device relocation (including interrupt binding) • Installation, configurations, and booting without user interventions • System address map construction by device-independent software Figure 1 illustrates the address line assignments during the configuration cycle. Figure 1. Address Lines During Configuration Cycle The SiI3114 only responds to Type 0 configuration cycles. Type 1 cycles, which pass a configuration request on to another PCI bus, are ignored. The address phase during a SiI3114 configuration cycle indicates the function number and register number being addressed which can be decoded by observing the status of the address lines AD[31:0]. The value of the signal lines AD[7:2] during the address phase of configuration cycles selects the register of the configuration space to access. Valid values are between 0 and 15, inclusive. Accessing registers outside this range results in an all-0s value being returned on reads, and no action being taken on writes. The Class Code register contains the Class Code, Sub-Class Code, and Register-Level Programming Interface registers. All writable bits in the configuration space except offset 44h, 8Ch are reset to their defaults by the hardware reset, PCI RESET (RST#) asserted. After reset, the SiI3114 is disabled and will only respond to PCI configuration write and PCI configuration read cycles. Deviations from the Specification The SiI3114 product has been developed and tested to the specification listed in this document. As a result of testing and customer feedback, we may become aware of deviations to the specification that could affect the component's operation. To ensure awareness of these deviations by anyone considering the use of the SiI3114, we have included an Errata section at the end of this specification. Please ensure that the Errata section is 31 11 10 8 7 2 1 0 Bit Number Don’t Care Bit Number 3-Bit Function Number 6-Bit Register Number 2-Bit Type Number |
Similar Part No. - SII3114CTU |
|
Similar Description - SII3114CTU |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
