 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SII1161CTU Datasheet(PDF) 9 Page - Silicon image |
|
||||||||||||||||||||||||||||||
SII1161CTU Datasheet(HTML) 9 Page - Silicon image |
|
|
9 / 46 page  SiI 1161 PanelLink Receiver Data Sheet 5 SiI-DS-0096-D General AC Specifications Table 2. General AC Specifications Symbol Parameter Conditions Min Typ Max Units Notes TDPS Intra-Pair (+ to -) Differential Input Skew 165MHz 245 ps 1 TCCS Channel to Channel Differential Input Skew 165MHz 4 ns 1 TIJIT Worst Case Differential Input Clock Jitter 65 MHz 465 ps 2,3 tolerance 112 MHz 270 ps 165 MHz 182 ps RCIP ODCK Cycle Time (one pixel per clock) 6 40 ns 1 FCIP ODCK Frequency (one pixel per clock) one pixel per clock 25 165 MHz 1 RCIP ODCK Cycle Time (two pixels per clock) 12 80 ns 1 FCIP ODCK Frequency (two pixels per clock) two pixels per clock 12.5 82.5 MHz 1 TDUTY Output Clock Duty Cycle 40% 60% 7 TPDL Delay PD# / PDO# Low to high-Z outputs 10 ns 1 THSC Link disabled (DE inactive) to SCDT low 50 ms 1 TFSC Link enabled (DE active) to SCDT high 4 10 DEedges 1 TCLKPD Delay from RXC+ Inactive to high-Z outputs 10 µs TCLKPU Delay from RXC+ active to data active 100 µs TST ODCK high to even data output 0.25 RCIP 1 TI2CDVD SDA Data Valid Delay from SCL high to low transition CL = 400pf 700 ns 5 TCTLW Control Pulse Width 2 RCIP 6 TRESET PD# Signal Low Time required for a valid I 2C reset 10 µs 1 Notes 1. Guaranteed by design. 2. Jitter defined per DVI 1.0 Specification, Section 4.6 – Jitter Specification. 3. Jitter measured with Clock Recovery Unit per DVI 1.0 Specification, Section 4.7 – Electrical Measurement Procedures. 4. Measured with transmitter powered down. 5. All Standard Mode I 2C (100kHz and 400kHz) timing requirements are guaranteed by design. 6. Control pulses include HSYNC, VSYNC, CTL1, CTL2 and CTL3. Pulses narrower than this minimum width specification are filtered out in the receiver and will not be seen at the output pins. 7. ODCK duty cycle is independent of the differential input clock duty cycle and the transmitter IDCK duty cycle. DC and AC parameters specific to the operating mode of the SiI 1161 are listed on the following pages. The output pin timing specifications are dependent on the selection of output drive capability. Specifications are listed for two modes: SiI 161B mode, which requires no I2C initialization; and SiI 1161 mode, which allows for optimization of input data recovery and output drive using I 2C programming. Designers should choose the mode most suited to their board-level requirements. |
Similar Part No. - SII1161CTU |
|
Similar Description - SII1161CTU |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
