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CC2520RHDR Datasheet(PDF) 45 Page - Texas Instruments |
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CC2520RHDR Datasheet(HTML) 45 Page - Texas Instruments |
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45 / 134 page  CC2520 DATASHEET 2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER SWRS068 – DECEMBER 2007 WWW.TI.COM 45 OPCODE Inputs Outputs Description Possible exceptions SXOSCOFF Command strobe s[7:0] Turn off the crystal oscillator. If the RF section is not idle a USAGE_ERROR is generated. If a frame is currently being received a RX_FRM_ABORTED exception is raised. USAGE_ERROR RX_FRM_ABORTED SFLUSHRX Command strobe s[7:0] Flush the RX FIFO and reset the demodulator. If a frame is currently being received a RX_FRM_ABORTED exception is raised. RX_FRM_ABORTED SFLUSHTX Command strobe s[7:0] Flush the TX FIFO SACK Command strobe s[7:0] Send acknowledgement frame, with the frame pendig subfield cleared, following reception of the current frame. Raises USAGE_ERROR exception if a frame is currently not being received. In this case no ACK frame is sent. USAGE_ERROR SACKPEND Command strobe s[7:0] Send acknowledgement frame, with the frame pendig subfield set, following reception of the current frame. Raises USAGE_ERROR exception if a frame is currently not being received. In this case no ACK frame is sent. USAGE_ERROR SNACK Command strobe s[7:0] Do not send an acknowledgement frame to the currently received frame, even if the rfr_autoack is set. Raises USAGE_ERROR exception if a frame is currently not being received. In this case no ACK frame is sent. USAGE_ERROR SRXMASKBITSET Command strobe s[7:0] Set bit 13 in the RXMASK. SRXMASKBITCLR Command strobe s[7:0] Clear bit 13 in the RXMASK. Raises RXENABLE_ZERO exception if this causes the RXENABE registers to be zero. RXENABLE_ZERO RXMASKOR d[15:0] s[7:0] Perform bitwise OR between RX enable mask and D. RXMASKAND d[15:0] s[7:0] Perform bitwise AND between RX enable mask and D. Raises RXENABLE_ZERO exception if this causes the RXENABLE registers to be zero. RXENABLE_ZERO Data IO BSET a[7:3] b[2:0] s[7:0] Set a single bit. Writes 1 to bit B in address A. This is done without affecting the value of, or triggering side- effects of other bits at the same address. Only the address range [0, 31] is accessible with this instruction. MEMADDR_ERROR BCLR a[7:3] b[2:0] s[7:0] Clear a single bit. Writes 0 to bit B in address A. This is done without affecting the value of, or triggering side- effects of other bits at the same address. Only the address range [0, 31] is accessible with this instruction. MEMADDR_ERROR MEMRD a[11:0] s[7:0] d[7:0] ... Read memory. The n’th byte of data D is read from address (A+n). Note that when an address with LSB=0 is read the content of the corresponding address with LSB=1 is buffered. If that address is read immediately after within the same MEMRD instruction, the buffered copy is read. In this way a read of a complete 16 bit word is performed as an atomic operation. MEMADDR_ERROR MEMWR a[11:0] d[7:0] ... s[7:0] d[7:0] ... Write memory. The n’th byte of data D input with the instruction is written to address (A+n). In addition, the n’th byte of data D output from the instruction is the unaltered data read from the memory location (A+n). MEMADDR_ERROR REGRD a[5:0] s[7:0] d[7:0] ... Same functionality as MEMRD, except the operation can only be started from addresses below 0x40. MEMADDR_ERROR |
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