ADS6225IRGZT datasheet(10/75 Pages) TI

Part #	ADS6225IRGZT

Description	DUAL CHANNEL, 12-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS INTERFACE

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DCLKP

DCLKM

CLKM

CLKP

FCLKM

FCLKP

DOP

DOM

Sample N–1

t

A

t

PD_CLK

Sample

N

Sample

N+11

Sample

N+12

Sample

N+13

Input

Signal

Input

Clock

Bit

Clock

Output

Data

Frame

Clock

D11

D7

D3

D9

D5

D1

D10

D6

D2

D8

D4

D0

Latency 12 Clocks

Sample N

T0105-03

ADS6225

,, ADS6224

ADS6223, ADS6222

SLAS543A – MAY 2007 – REVISED SEPTEMBER 2007

TIMING SPECIFICATIONS (continued)

Typical values are at 25

°C, min and max values are across the full temperature range T

MIN = –40°C to TMAX = 85°C, AVDD =

LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF , IO = 3.5 mA,

RL = 100 Ω , no internal termination, unless otherwise noted.

ADS6225

ADS6224

ADS6223

ADS6222

TEST

PARAMETER

UNIT

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

Bit clock and

From +100 mV to

tFALL

Frame clock

50

100

200

50

100

200

50

100

200

50

100

200

ps

–100 mV

fall time

LVDS Bit

clock duty

45%

50%

55%

45%

50%

55%

45%

50%

55%

45%

50%

55%

cycle

LVDS Frame

clock duty

47%

50%

53%

47%

50%

53%

47%

50%

53%

47%

50%

53%

cycle

Figure 1. Latency

10

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Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

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ADS6225IRGZT Datasheet(PDF) 10 Page - Texas Instruments

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