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TSC2101 Datasheet(PDF) 19 Page - Texas Instruments |
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TSC2101 Datasheet(HTML) 19 Page - Texas Instruments |
19 / 95 page TSC2101 SLAS392D− JUNE 2003 − REVISED MAY 2005 www.ti.com 19 D Word Select Signals The word select signal (WCLK) indicates the channel being transmitted: — WCLK = 0: left channel for I2S mode; — WCLK = 1: right channel for I2S mode. For other modes refer to the timing diagrams below. D Bitclock (BCLK) Signal In addition to being programmable as master or slave mode, the BCLK can also be configured in two transfer modes, 256-S transfer mode and continuous transfer mode, which are described below. These modes are set using bit D12 of control register 06H/page 2. D 256-S Transfer Mode In the 256-S mode, the BCLK rate always equals 256 times the WCLK frequency. In the 256-S mode, the combination of ADC/DAC sampling rate equal to Fsref (as selected by bit D5D0 of control register 00H/page 2) and left-justified mode is not supported. If IOVDD is equal to 1.1 V, then ADC/DAC sampling rate should be less than 39 kHz for all modes except the left justified mode where it should be less than 24 kHz. D Continuous Transfer Mode In the continuous transfer mode, the BCLK rate always equals two-word length times the frequency of WCLK. D Right Justified Mode In right-justified mode, the LSB of left channel is valid on the rising edge of BCLK preceding, the falling edge on WCLK. Similarly the LSB of right channel is valid on the rising edge of BCLK preceding the rising edge of WCLK. BCLK WCLK SDIN/ SDOUT n n−1 1 0 0 n n−1 1 0 1/fs LSB MSB Left Channel Right Channel n−22 2 n−2 Figure 15. Timing Diagram for Right-Justified Mode |
Similar Part No. - TSC2101_08 |
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Similar Description - TSC2101_08 |
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