4 / 12 page
CY8C20110
Document Number: 001-17345 Rev. *B
Page 4 of 12
Figure 2. Pin Diagram - 16 SOIC
GP0[3]
1
2
3
4
5
6
7
8
SOIC
(Top View)
VDD
VSS
GP0[4]
GP0[0]
GP0[1]
I2CSCL
I2CSDA
GP1[0]
GP1[3]
GP1[4]
GP0[2]
XRES
16
15
14
13
12
11
10
9
CSInt
GP1[1]
GP1[2]
Table 2. Pin Definitions - 16 SOIC
Pin Number
Name
Description
1
GP0[3]
Configurable as CapSense or GPIO
2
CSInt
Integrating Capacitor Input
3
GP0[4]
Configurable as CapSense or GPIO
4
GP0[0]
Configurable as CapSense or GPIO
5
GP0[1]
Configurable as CapSense or GPIO
6I2C SCL
I2C clock
7I2C SDA
I2C data
8
GP1[0]
Configurable as CapSense or GPIO
9
GP1[1]
Configurable as CapSense or GPIO
10
VSS
Ground connection
11
GP1[2]
Configurable as CapSense or GPIO
12
GP1[3]
Configurable as CapSense or GPIO
13
GP1[4]
Configurable as CapSense or GPIO
14
XRES
Active HIGH external reset with internal pull down.
15
GP0[2]
Configurable as CapSense or GPIO
16
VDD
Supply voltage
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
