ACS8520AT datasheet(30/150 Pages) SEMTECH

Part #	ACS8520AT

Description	Synchronous Equipment Timing Source for Stratum 3/4E/4 and SMC Systems

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ACS8520A SETS

ADVANCED COMMS & SENSING

FINAL

DATASHEET

Revision 1.00/September 2007© Semtech Corp.

Page 30

www.semtech.com

For direct hardware control of Master or Slave operation

the Master/Slave control pin (MSTSLVB) can be used to

externally control some of these functions according to

Table 12. These functions can also be controlled via

software.

Whilst the Master and Slave outputs could be cross-

connected and connected to any input on the alternative

device, input I11 has been chosen as the input controlled

by the MSTSLVB pin.

Alignment of Priority Tables in Master and Slave

ACS8520A

In a redundant system where the Slave is normally locked

to the Master device, if the Master device fails the Slave

device must revert to locking to the same external

reference that the Master was locked to. This will ensure

that minimum disturbance, both in frequency and phase,

is created on the output of the Slave device due to the

failure of the Master device. As stated previously

(Table 11), it is recommended that the programmed

priorities of the reference sources are the same in both

devices, apart from the Master/Slave cross-connect

inputs.

Both devices can also monitor all their reference sources

and determine the validity of each source. It is

recommended that the availability of valid sources are

also aligned between the two devices. This is achieved by

writing the value, as reported by sts_sources_valid

Reg. 0E & 0F), from one device into the

cnfg_sts_remote_sources_valid register (Reg. 30 and 31)

of the other. This will ensure that any source considered

invalid by one device is also considered invalid by the

other. If a failure of the Master does occur, this will ensure

that the Slave will always select the reference that the

Master was locked to.

T4 Generation in Master and Slave ACS8520A

As specified by the I.T.U., there is no need to align the

phases of the T4 outputs in Master and Slave devices. For

a fully redundant system, there is a need, however, to

ensure that all devices select the same reference source.

As there is no need to guarantee the alignment of phase

of the T4 outputs, the Slave devices T4 input does not

need to lock to the Masters T4 output, but only needs to

ensure that it locks to the same external reference

source. The actions of aligning the priority tables and

available reference sources performed for the T0 outputs

will be equally valid for the T4 outputs. The only difference

being that the input connected to the Master's output is

disabled for the T4 path (allowing it only to lock to external

references). This can be easily achieved as the T4 and T0

paths have separate programmed priorities. There is no

defined Holdover requirement for the T4 path.

Alignment of the Output Clock Phases in Master

and Slave ACS8520A

When the

ACS8520A is locked to a reference source of

frequency f, the output clocks of frequency f will be in-

phase with the reference source (with Phase Build-out

disabled). As all T0 output clocks from the

ACS8520A

are derived from the same T0 frequency, any frequency

greater than f at the output will be “falling edge aligned”

with the output at frequency f. Any frequency less than f

will be effectively a division of f, if possible. Similarly for

T4, all T4 output clocks will be phase-related to the T4

input.

The effect of this relationship is that if the Master and

Slave devices are cross-connected with 19.44 MHz

clocks, their output clocks at 19.44 MHz, 38.88 MHz,

77.76 MHz, 155.52 MHz & 311.04 MHz will be aligned

between the 2 devices. However, their outputs of

6.48 MHZ, 1.544 MHz, 2.048 MHz, 2 kHz and 8 kHz etc.

would not necessarily be aligned. Whilst most

applications would not be affected by the non-alignment

of most of these clocks, the non-alignment of the 2 kHz

and/or the 8 kHz may cause framing errors.

0 =

Slave

Priority of

input I11

1 (highest priority).

When a Slave, this

input is designated

as that connected to

the output of the

Master.

Phase

Build-out

Disabled.

This ensures that the

Slave locks to the

Master with the

minimum phase

offset possible.

Revertive

mode

Enabled

This ensures that the

Slave always locks to

the Master when it is

available.

T0 DPLL

bandwidth

Forced to the

acquisition

bandwidth setting.

A higher bandwidth

on the Slave ensures

closer phase

tracking.

Table 12 MSTSLVB Pin Operation (cont...)

MSTSLVB

Feature

Setting

Reason

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