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NCP3101 Datasheet(PDF) 6 Page - ON Semiconductor |
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NCP3101 Datasheet(HTML) 6 Page - ON Semiconductor |
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6 / 18 page  NCP3101 http://onsemi.com 6 DETAILED OPERATING DESCRIPTION General NCP3101 is a high efficiency integrated wide input voltage 6 A synchronous PWM buck converter designed to operate from a 4.5 V to 13.2 V supply. The output voltage of the converter can be precisely regulated down to 800 mV $1.0% when the VFB pin is tied to VOUT. The switching frequency is internally set to 275 kHz. A high gain Operational Transconductance Error Amplifier (OTA) is used for feedback and stabilizing the loop. Duty Cycle and Maximum Pulse Width Limits In steady state DC operation, the duty cycle will stabilize at an operating point defined by the ratio of the input to the output voltage. The NCP3101 can achieve an 80% duty cycle. There is a built in off-time which ensures that the bootstrap supply is charged every cycle. The NCP3101, which is capable of a 100 nsec pulse width (minimum), can allow a 12 V to 0.8 V conversion at 275 kHz. The duty cycle limit and the corresponding output voltage are shown below in graphical format in Figure 9 and 11. The light gray area represents the safe operating area for the lowest maximum operational duty cycle and the dark grey area represents the absolute maximum duty cycle and corresponding output voltage. Figure 9. Duty Cycle to Output Voltage OUTPUT VOLTAGE (V) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.8 2.8 4.8 6.8 8.8 10.8 Minimum 4.5 V 13.2 V Max-Maximum Min-Maximum Input Voltage Range (VCC and BST) The input voltage range for both VCC and BST is 4.5 V to 13.2 V with reference to GND and PHS, respectively. Although BST is rated at 13.2 V with reference to PHS, it can also tolerate 25 V with respect to GND. Figure 10. Maximum Input to Output Voltage INPUT VOLTAGE (V) 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 10 9 8 7 6 5 4 3 DMAX = 0.7 DMAX = 0.8 11 External Enable/Disable When the Comp Pin voltage falls or is pulled externally below the 400 mV threshold as shown in Figure 11, it disables the PWM Logic and the gate drive outputs. In this disabled mode, the operational transconductance amplifier's (EOTA) output source current is reduced and limited to the Soft-Start mode of 10 mA. Figure 11. Disable Circuit - + 16 17 COMP/DIS VREF 0.8 V FB Normal Shutdown Behavior Normal shutdown occurs when the IC stops switching because the input supply reaches UVLO threshold. In this case, switching stops, the internal soft-start, SS, is discharged, and all GATE pins go low. The switch node enters a high impedance state and the output capacitors discharge through the load with no ringing on the output voltage. |
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