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Serial Audio Input Ports

th1

tsu1

tsu2

th2

DATA

BCLK

(Input)

LRCLK

(Input)

APPLICATION INFORMATION

AUDIO SERIAL INTERFACE

AUDIO DATA FORMATS AND TIMING

TPA5050

SLOS492B – MAY 2006 – REVISED MAY 2007

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

1.024

12.288

MHz

Setup time, LRCLK to BCLK rising edge

10

ns

Hold time, LRCLK from BCLK rising edge

10

ns

Setup time, DATA to BCLK rising edge

10

ns

Hold time, DATA from BCLK rising edge

10

ns

LRCLK frequency

32

48

192

kHz

BCLK duty cycle

50%

LRCLK duty cycle

50%

BCLK rising edges between LRCLK rising edges

LRCLK duty cycle = 50%

32

64

BCLK edges

Figure 3. Serial Data Interface Timing

The audio serial interface for the TPA5050 consists of a 3-wire synchronous serial port. It includes LRCLK,

BCLK, and DATA. BCLK is the serial audio bit clock, and it is used to clock the serial data present on DATA into

the serial shift register of the audio interface. Serial data is clocked into the TPA5050 on the rising edge of

BCLK. LRCLK is the serial audio left/right word clock. It is used to latch serial data into the internal registers of

the serial audio interface. LRCLK is operated at the sampling frequency, fs. BCLK can be operated at 32 to 64

the operation of the TPA5050.

Table 1).

5

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