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DS4100H Datasheet(PDF) 5 Page - Maxim Integrated Products |
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DS4100H Datasheet(HTML) 5 Page - Maxim Integrated Products |
5 / 6 page 100MHz HCSL Clock Generator _______________________________________________________________________________________ 5 Pin Description PIN NAME FUNCTION 1 OE Output Enable. On-chip pullup resistor. If connected to logic-high or left open, the clock output is enabled. If connected to logic-low, the output is three-stated. 2 RREF Connect a 475 ±1% resistor from RREF to ground. 3 GND Ground 4 OUTP Positive Clock Output. Requires a series resistor and a pulldown resistor. 5 OUTN Negative Clock Output. Requires a series resistor and a pulldown resister. 6 VCC +3.3V Supply Input. Device power can range from 3.135V to 3.465V. 7–10 N.C. No Connection — EP Exposed Paddle. The exposed pad must be used for thermal relief. This pad can be connected to ground. OUTPUT BUFFER RECEIVER RS Z0 CL Z0 = 50 Ω, 35in LENGTH RT RT RT = 50 Ω RS OUTP OUTN RS = 0 Ω FOR TEST, 0 TO 33Ω TO MINIMIZE RINGING IN APPLICATION. CL = SIMULATES RECEIVER INPUT CAPACITANCE FOR TEST ONLY. OUTP OUTN Z0 CL CL = 2pF Figure 2. Typical Termination for HCSL Driver and Test Conditions OE OUTP tPZH tPZ 0.7 x VCC 0.3 x VCC GND GND OUTN tPZL Figure 3. HCSL Output Timing Diagram When OE is Enabled and Disabled |
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Similar Description - DS4100H |
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