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TC4027BP Datasheet(PDF) 4 Page - Toshiba Semiconductor

Part No. TC4027BP
Description  Dual J-K Master-Slave Flip Flop
Download  9 Pages
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Maker  TOSHIBA [Toshiba Semiconductor]
Homepage  http://www.semicon.toshiba.co.jp/eng
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TC4027BP Datasheet(HTML) 4 Page - Toshiba Semiconductor

   
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TC4027BP/BF/BFN
2007-10-01
4
Dynamic Electrical Characteristics (Ta = 25°C, VSS = 0 V, CL = 50 pF)
Test Condition
Characteristics
Symbol
VDD (V)
Min
Typ.
Max
Unit
Output transition time
(low to high)
tTLH
5
10
15
70
35
30
200
100
80
ns
Output transition time
(high to low)
tTHL
5
10
15
70
35
30
200
100
80
ns
Propagation delay time
(CLOCK-Q, Q )
tpLH
tpHL
5
10
15
150
75
60
300
130
90
ns
Propagation delay time
(SET, RESET-Q, Q )
tpLH
tpHL
5
10
15
120
60
45
300
130
90
ns
Max clock frequency
fCL
5
10
15
3.5
8.0
12.0
8
16
20
MHz
Max clock input rise time
Max clock input fall time
trCL
tfCL
5
10
15
No limit
μs
Min pulse width
(SET, RESET)
tW
5
10
15
60
35
25
180
80
50
ns
Min clock pulse width
tW
5
10
15
60
35
25
140
60
40
ns
Min set-up time
(J, K-CLOCK)
tSU
5
10
15
30
10
5
140
50
35
ns
Min hold time
(J, K-CLOCK)
tH
5
10
15
140
50
35
ns
Min removal time
(SET, RESET-CLOCK)
trem
5
10
15
40
20
15
ns
Input capacitance
CIN
5
7.5
pF


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