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M36W0R6030T0 Datasheet(PDF) 4 Page - STMicroelectronics

Part No. M36W0R6030T0
Description  64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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M36W0R6030T0 Datasheet(HTML) 4 Page - STMicroelectronics

 
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SUMMARY DESCRIPTION
The M36W0R6030T0 and M36W0R6030B0 com-
bine two memory devices in a Multi-Chip Package:
a 64-Mbit, Multiple Bank Flash memory, the
M58WR064FT/B, and an 8-Mbit SRAM. Recom-
mended operating conditions do not allow more
than one memory to be active at the same time.
The memory is offered in a Stacked TFBGA88
(8 x 10mm, 8x10 ball array, 0.8mm pitch) pack-
age.
In addition to the standard version, the packages
are also available in Lead-free version, in compli-
ance with JEDEC Std J-STD-020B, the ST ECO-
PACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive.
All packages are compliant with Lead-free solder-
ing processes.
is supplied with all the bits erased (set to ‘1’).
Figure 2. Logic Diagram
Table 1. Signal Names
Note: 1. A21-A19 are not connected to the SRAM component.
AI08534C
22
A0-A21
DQ0-DQ15
M36W0R6030T
M36W0R6030B
GF
16
WF
RPF
WPF
E1S
GS
WS
UBS
LBS
VSS
VDDF
VPPF
VDDS
WAITF
LF
KF
VDDQ
EF
E2S
A0-A21 (1)
Address Inputs
DQ0-DQ15
Common Data Input/Output
VDDF
Flash Memory Power Supply
VDDQ
Common Flash and SRAM Power
Supply for I/O Buffers
VPPF
Common Flash Optional Supply
Voltage for Fast Program and Erase
VSS
Ground
VDDS
SRAM Power Supply
NC
Not Connected Internally
DU
Do Not Use as Internally Connected
Flash Memory Signals
LF
Latch Enable input
EF
Chip Enable input
GF
Output Enable input
WF
Write Enable input
RPF
Reset input
WPF
Write Protect input
KF
Burst Clock
WAITF
Wait Data in Burst Mode
SRAM Signals
E1S, E2S
Chip Enable input
GS
Output Enable input
WS
Write Enable input
UBS
Upper Byte Enable input
LBS
Lower Byte Enable input


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