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M36W0R6030T0 Datasheet(PDF) 11 Page - STMicroelectronics

Part No. M36W0R6030T0
Description  64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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M36W0R6030T0 Datasheet(HTML) 11 Page - STMicroelectronics

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M36W0R6030T0, M36W0R6030B0
SRAM OPERATIONS
There are five standard operations that control the
device. These are Read, Write, Standby/Power-
down, Data Retention and Output Disable.
Read. Read operations are used to output the
contents of the SRAM Array.
The device is in Byte Read mode whenever Write
Enable, WS, is at VIH, Output Enable, GS, is at VIL,
Chip Enable, E1S, is at VIL, Chip Enable, E2S, is at
VIH, and UBS or LBS is at VIL.
The device is in Word Read mode whenever Write
Enable, WS, is at VIH, Output Enable, GS, is at VIL,
Byte Enable inputs UBS and LBS are both at VIL
and the two Chip Enable inputs, E1S, and E2S are
Don’t Care.
The Read and Standby AC Waveforms are shown
in Figures 9 and 10, respectively and the parame-
ters are given in Table 9., Read AC Characteris-
tics.
Write. Write operations are used to write data to
the SRAM. The device is in Write mode whenever
WS, E1S and UBS and/or LBS are at VIL, and E2S
is at VIH. All these signals must be asserted to ini-
tiate a Write cycle. The data is latched on the fall-
ing edge of E1S, the rising edge of E2S, the falling
edge of WS, or the falling edge of UBS and/or LBS,
whichever occurs last. The Write cycle will termi-
nate on the rising edge of E1S, the rising edge of
WS, the rising edge of UBS and/or LBS, or the fall-
ing edge of E2S, whichever occurs first. The tim-
ings are referenced to the signal that terminates
the Write cycle.
The outputs are disabled during Write cycles
(whenever E1S, at VIL, E2S at VIH, and WS at VIL).
The Write AC Waveforms are shown in Figures
11, 12, 13 and 14, while Table 10. gives the Write
AC Characteristics.
Standby/Power-Down. The device automatically
enters the Standby/Power-Down mode when
DQ0-DQ15 are not toggling, reducing the power
consumption to the Standby level, ISB.
The device is also in Standby/Power-Down mode
whenever E1S is at VIH, E2S is at VIL or both UBS
and LBS are at VIH. The outputs then become high
impedance.
The Standby AC Waveforms are shown in Figure
10. See Table 9., Read AC Characteristics, for
timings.
Data Retention. The data retention mode is en-
tered tCDR after de-asserting E1S, E2S or UBS and
LBS. The data retention performance as VDD goes
down to VDR is described in Table 11., Figures 15
and 16, SRAM Low VDD Data Retention AC Wave-
forms, E1S or UBS / LBS Controlled and SRAM
Low VDD Data Retention AC Waveforms, E2S
Controlled, respectively.
Output Disable. The device is in the Output Dis-
able mode whenever GS, is at VIH. In this mode,
DQ0-DQ15 are high impedance.


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