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GS1582 Datasheet(PDF) 26 Page - Gennum Corporation |
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GS1582 Datasheet(HTML) 26 Page - Gennum Corporation |
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26 / 114 page  GS1582 Data Sheet 40117 - 1 November 2007 26 of 114 4.2 Parallel Data Inputs Data is clocked into the device on the rising edge of PCLK as shown in Figure 4-1. The input data format is defined by the setting of the external SD/HD, SMPTE_BYPASS, and DVB_ASI pins and may be presented in 10-bit or 20-bit format. The input data bus width is controlled by the 20bit/10bit input pin. Figure 4-1: PCLK to Data Timing 4.2.1 Parallel Input in SMPTE Mode When the device is operating in SMPTE mode, see SMPTE Mode on page 28, both SD and HD data may be presented to the input bus in either multiplexed or demultiplexed form depending on the setting of the 20bit/10bit input pin. In 20-bit mode, (20bit/10bit = HIGH), the input data format should be word aligned, demultiplexed luma and chroma data. Luma words should be presented on DIN[19:10] while chroma words should be presented on DIN[9:0]. In 10-bit mode, (20bit/10bit = LOW), the input data format should be word aligned, multiplexed luma and chroma data. The data should be presented on DIN[19:10]. DIN[9:0] will be high impedance in this mode. 4.2.2 Parallel Input in DVB-ASI Mode When operating in DVB-ASI mode, see DVB-ASI mode on page 34, the GS1582 must be set to 10-bit operation mode by setting the 20bit/10bit pin LOW. The device will accept 8-bit data words on DIN[17:10]. DIN17 = HIN is the most significant bit of the encoded transport stream data and DIN10 = AIN is the least significant bit. In addition, DIN19 and DIN18 will be configured as the DVB-ASI control signals INSSYNCIN and KIN respectively. See DVB-ASI mode on page 34 for a description of these DVB-ASI specific input signals. DIN[9:0] will have a Logic Level HIGH in DVB-ASI mode. PCLK DIN[19:0] DATA Control signal input tSU tIH |
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