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L6743 Datasheet(PDF) 8 Page - STMicroelectronics |
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L6743 Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 17 page Device description and operation L6743, L6743Q 8/17 5.1 High-impedance (HiZ) management The Driver is able to manage High-Impedance state by keeping all MOSFETs in off state in two different ways. ● If the EN signal is pulled low, the device will keep all mosfets OFF careless of the PWM status. ● When EN is asserted, if the PWM signal remains in the HiZ window for a time longer than the hold-off time, the device detects the HiZ condition so turning off all the MOSFETs. The HiZ window is defined as the PWM voltage range comprised between VPWM_IL and VPWM_IH. The device exits from the HiZ state only after a PWM transition to logic zero (VPWM < VPWM_IL). See Figure 4 for details about HiZ timings. The implementation of the High-Impedance state allows the controller that will be connected to the driver to manage High-Impedance state of its output, avoiding to produce negative undershoot on the regulated voltage during the shut-down stage. Furthermore, different power management states may be managed such as pre-bias start-up. 5.2 Preliminary OV protection After VCC has overcome its UVLO threshold and while in HiZ, L6743, L6743Q activates the Preliminary-OV protection. The intent of this protection is to protect the load especially from High-Side MOSFET failures during the system start-up. In fact, VRM, and more in general PWM controllers, have a 12V bus compatible turn-on threshold and results to be non-operative if VCC is below that turn-on thresholds (that results being in the range of about 10V). In case of a High-Side mosfet failure, the controller won’t recognize the over voltage until VCC = ~10V (unless other special features are implemented): but in that case the output voltage is already at the same voltage (~10V) and the load (CPU in most cases) already burnt. L6743, L6743Q by-pass the PWM controller by latching on the Low-Side MOSFET in case the PHASE pin voltage overcome 2V during the HiZ state. When the PWM input exits form the HiZ window, the protection is reset and the control of the output voltage is transferred to the controller connected to the PWM input. Since the Driver has its own UVLO threshold, a simple way to provide protection to the output in all conditions when the device is OFF consists in supplying the controller through the 5VSB bus: 5VSB is always present before any other voltage and, in case of High-Side short, the Low-Side mosfet is driven with 5V assuring a reliable protection of the load. Preliminary OV is active after UVLO and while the Driver is in HiZ state and it is disabled after the first PWM transition. The controller will have to manage its output voltage from that time on. |
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